597 lines
20 KiB
C
597 lines
20 KiB
C
#include "../../../gfx.h"
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#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
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#undef Red
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#undef Green
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#undef Blue
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#endif
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#include "stm32f746g_discovery_sdram.h"
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#include "stm32f7xx_hal_rcc.h"
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#include "stm32f7xx_hal_dma.h"
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#include "stm32f7xx_hal_gpio.h"
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#include "stm32f7xx_hal_sdram.h"
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#if GFX_USE_OS_CHIBIOS
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#define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
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#endif
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#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
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#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
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#define REFRESH_COUNT ((gU32)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
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#define SDRAM_TIMEOUT ((gU32)0xFFFF)
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/* DMA definitions for SDRAM DMA transfer */
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#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
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#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
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#define SDRAM_DMAx_STREAM DMA2_Stream0
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#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
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/* FMC SDRAM Mode definition register defines */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
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static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, gU32 RefreshCount);
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static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
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static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
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static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
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static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, gU32 Bank);
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static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout);
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static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, gU32 RefreshRate);
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static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
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{
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/* Check the SDRAM handle parameter */
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if(hsdram == NULL)
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return;
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if(hsdram->State == HAL_SDRAM_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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hsdram->Lock = HAL_UNLOCKED;
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}
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/* Initialize the SDRAM controller state */
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hsdram->State = HAL_SDRAM_STATE_BUSY;
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/* Initialize SDRAM control Interface */
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_FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
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/* Initialize SDRAM timing Interface */
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_FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
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/* Update the SDRAM controller state */
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hsdram->State = HAL_SDRAM_STATE_READY;
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}
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static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
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{
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gU32 tmpr1 = 0;
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gU32 tmpr2 = 0;
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/* Set SDRAM bank configuration parameters */
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if (Init->SDBank != FMC_SDRAM_BANK2)
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{
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tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
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/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
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tmpr1 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
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FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
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FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
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tmpr1 |= (gU32)(Init->ColumnBitsNumber |\
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Init->RowBitsNumber |\
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Init->MemoryDataWidth |\
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Init->InternalBankNumber |\
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Init->CASLatency |\
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Init->WriteProtection |\
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Init->SDClockPeriod |\
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Init->ReadBurst |\
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Init->ReadPipeDelay
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);
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Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
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}
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else /* FMC_Bank2_SDRAM */
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{
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tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
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/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
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tmpr1 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
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FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
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FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
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tmpr1 |= (gU32)(Init->SDClockPeriod |\
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Init->ReadBurst |\
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Init->ReadPipeDelay);
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tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
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/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
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tmpr2 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
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FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
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FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
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tmpr2 |= (gU32)(Init->ColumnBitsNumber |\
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Init->RowBitsNumber |\
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Init->MemoryDataWidth |\
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Init->InternalBankNumber |\
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Init->CASLatency |\
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Init->WriteProtection);
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Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
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Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
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}
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return HAL_OK;
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}
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static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, gU32 Bank)
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{
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gU32 tmpr1 = 0;
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gU32 tmpr2 = 0;
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/* Set SDRAM device timing parameters */
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if (Bank != FMC_SDRAM_BANK2)
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{
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tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
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/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
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tmpr1 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
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FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
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FMC_SDTR1_TRCD));
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tmpr1 |= (gU32)(((Timing->LoadToActiveDelay)-1) |\
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(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
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(((Timing->SelfRefreshTime)-1) << 8) |\
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(((Timing->RowCycleDelay)-1) << 12) |\
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(((Timing->WriteRecoveryTime)-1) <<16) |\
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(((Timing->RPDelay)-1) << 20) |\
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(((Timing->RCDDelay)-1) << 24));
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Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
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}
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else /* FMC_Bank2_SDRAM */
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{
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tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
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/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
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tmpr1 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
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FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
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FMC_SDTR1_TRCD));
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tmpr1 |= (gU32)(((Timing->LoadToActiveDelay)-1) |\
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(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
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(((Timing->SelfRefreshTime)-1) << 8) |\
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(((Timing->WriteRecoveryTime)-1) <<16) |\
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(((Timing->RCDDelay)-1) << 24));
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tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
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/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
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tmpr2 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
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FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
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FMC_SDTR1_TRCD));
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tmpr2 |= (gU32)((((Timing->RowCycleDelay)-1) << 12) |\
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(((Timing->RPDelay)-1) << 20));
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Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
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Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
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}
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return HAL_OK;
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}
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/**
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* @brief Initializes the SDRAM device.
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* @retval SDRAM status
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*/
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void BSP_SDRAM_Init(void)
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{
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SDRAM_HandleTypeDef sdramHandle;
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FMC_SDRAM_TimingTypeDef Timing;
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/* SDRAM device configuration */
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sdramHandle.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
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Timing.LoadToActiveDelay = 2;
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Timing.ExitSelfRefreshDelay = 7;
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Timing.SelfRefreshTime = 4;
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Timing.RowCycleDelay = 7;
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Timing.WriteRecoveryTime = 2;
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Timing.RPDelay = 2;
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Timing.RCDDelay = 2;
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sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
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sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
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sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
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sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
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sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
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sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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/* SDRAM controller initialization */
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BSP_SDRAM_MspInit(&sdramHandle);
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_HAL_SDRAM_Init(&sdramHandle, &Timing);
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/* SDRAM initialization sequence */
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BSP_SDRAM_Initialization_sequence(&sdramHandle, REFRESH_COUNT);
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}
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static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout)
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{
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/* Check the SDRAM controller state */
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if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Update the SDRAM state */
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hsdram->State = HAL_SDRAM_STATE_BUSY;
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/* Send SDRAM command */
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_FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
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/* Update the SDRAM controller state state */
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if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
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{
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hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
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}
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else
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{
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hsdram->State = HAL_SDRAM_STATE_READY;
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}
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return HAL_OK;
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}
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static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout)
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{
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__IO gU32 tmpr = 0;
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gTicks tickstart = 0;
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/* Set command register */
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tmpr = (gU32)((Command->CommandMode) |\
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(Command->CommandTarget) |\
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(((Command->AutoRefreshNumber)-1) << 5) |\
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((Command->ModeRegisterDefinition) << 9)
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);
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Device->SDCMR = tmpr;
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/* Get tick */
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tickstart = gfxSystemTicks();
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/* wait until command is send */
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while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
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{
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/* Check for the Timeout */
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if(Timeout != HAL_MAX_DELAY)
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{
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if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout))
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{
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return HAL_TIMEOUT;
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}
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}
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, gU32 RefreshRate)
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{
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/* Check the SDRAM controller state */
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if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Update the SDRAM state */
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hsdram->State = HAL_SDRAM_STATE_BUSY;
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/* Program the refresh rate */
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_FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
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/* Update the SDRAM state */
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hsdram->State = HAL_SDRAM_STATE_READY;
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return HAL_OK;
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}
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static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, gU32 RefreshRate)
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{
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/* Set the refresh rate in command register */
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Device->SDRTR |= (RefreshRate<<1);
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return HAL_OK;
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}
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static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma)
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{
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gU32 tmp = 0;
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/* Check the DMA peripheral state */
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if(hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Get the CR register value */
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tmp = hdma->Instance->CR;
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/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
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tmp &= ((gU32)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
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DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
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DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
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DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
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/* Prepare the DMA Stream configuration */
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tmp |= hdma->Init.Channel | hdma->Init.Direction |
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hdma->Init.PeriphInc | hdma->Init.MemInc |
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hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
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hdma->Init.Mode | hdma->Init.Priority;
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/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
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if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
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{
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/* Get memory burst and peripheral burst */
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tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
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}
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/* Write to DMA Stream CR register */
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hdma->Instance->CR = tmp;
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/* Get the FCR register value */
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tmp = hdma->Instance->FCR;
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/* Clear Direct mode and FIFO threshold bits */
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tmp &= (gU32)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
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/* Prepare the DMA Stream FIFO configuration */
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tmp |= hdma->Init.FIFOMode;
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/* the FIFO threshold is not used when the FIFO mode is disabled */
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if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
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{
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/* Get the FIFO threshold */
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tmp |= hdma->Init.FIFOThreshold;
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}
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/* Write to DMA Stream FCR */
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hdma->Instance->FCR = tmp;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Initialize the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief DeInitializes the DMA peripheral
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @retval HAL status
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*/
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static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
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{
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/* Check the DMA peripheral state */
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if(hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the DMA peripheral state */
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if(hdma->State == HAL_DMA_STATE_BUSY)
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{
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return HAL_ERROR;
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}
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/* Disable the selected DMA Streamx */
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__HAL_DMA_DISABLE(hdma);
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/* Reset DMA Streamx control register */
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hdma->Instance->CR = 0;
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/* Reset DMA Streamx number of data to transfer register */
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hdma->Instance->NDTR = 0;
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/* Reset DMA Streamx peripheral address register */
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hdma->Instance->PAR = 0;
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/* Reset DMA Streamx memory 0 address register */
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hdma->Instance->M0AR = 0;
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/* Reset DMA Streamx memory 1 address register */
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hdma->Instance->M1AR = 0;
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/* Reset DMA Streamx FIFO control register */
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hdma->Instance->FCR = (gU32)0x00000021;
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/* Clear all flags */
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__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
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__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
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__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
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__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
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__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Initialize the DMA state */
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hdma->State = HAL_DMA_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hdma);
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|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Programs the SDRAM device.
|
|
* @param RefreshCount: SDRAM refresh counter value
|
|
* @retval None
|
|
*/
|
|
static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, gU32 RefreshCount)
|
|
{
|
|
FMC_SDRAM_CommandTypeDef Command;
|
|
|
|
/* Step 1: Configure a clock configuration enable command */
|
|
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
Command.AutoRefreshNumber = 1;
|
|
Command.ModeRegisterDefinition = 0;
|
|
|
|
/* Send the command */
|
|
_HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
|
|
|
|
/* Step 2: Insert 100 us minimum delay */
|
|
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
|
|
gfxSleepMilliseconds(1);
|
|
|
|
/* Step 3: Configure a PALL (precharge all) command */
|
|
Command.CommandMode = FMC_SDRAM_CMD_PALL;
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
Command.AutoRefreshNumber = 1;
|
|
Command.ModeRegisterDefinition = 0;
|
|
|
|
/* Send the command */
|
|
_HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
|
|
|
|
/* Step 4: Configure an Auto Refresh command */
|
|
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
Command.AutoRefreshNumber = 8;
|
|
Command.ModeRegisterDefinition = 0;
|
|
|
|
/* Send the command */
|
|
_HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
|
|
|
|
/* Step 5: Program the external memory mode register */
|
|
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
Command.AutoRefreshNumber = 1;
|
|
Command.ModeRegisterDefinition = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
|
|
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
|
|
SDRAM_MODEREG_CAS_LATENCY_2 |\
|
|
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
|
|
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;;
|
|
|
|
/* Send the command */
|
|
_HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
|
|
|
|
/* Step 6: Set the refresh rate counter */
|
|
/* Set the device refresh rate */
|
|
_HAL_SDRAM_ProgramRefreshRate(hsdram, RefreshCount);
|
|
}
|
|
|
|
/**
|
|
* @brief Initializes SDRAM MSP.
|
|
* @param hsdram: SDRAM handle
|
|
* @param Params
|
|
* @retval None
|
|
*/
|
|
static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
|
|
{
|
|
static DMA_HandleTypeDef dma_handle;
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
/* Enable FMC clock */
|
|
__HAL_RCC_FMC_CLK_ENABLE();
|
|
|
|
/* Enable chosen DMAx clock */
|
|
__DMAx_CLK_ENABLE();
|
|
|
|
/* Enable GPIOs clock */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
|
|
/* Common GPIO configuration - some are already setup by ChibiOS Init */
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
gpio_init_structure.Pull = GPIO_PULLUP;
|
|
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
|
gpio_init_structure.Alternate = GPIO_AF12_FMC;
|
|
|
|
/* GPIOC configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_3;
|
|
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
|
|
|
|
/* GPIOD configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |
|
|
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
|
|
|
|
/* GPIOE configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
|
|
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
|
GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
|
|
|
|
/* GPIOF configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
|
|
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
|
GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
|
|
|
|
/* GPIOG configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
|
|
GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
|
|
|
|
/* GPIOH configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
|
|
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
|
|
|
|
/* Configure common DMA parameters */
|
|
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
|
|
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
|
|
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
|
|
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
|
|
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
|
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
|
dma_handle.Init.Mode = DMA_NORMAL;
|
|
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
|
|
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
|
|
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
|
|
|
dma_handle.Instance = SDRAM_DMAx_STREAM;
|
|
|
|
/* Associate the DMA handle */
|
|
__HAL_LINKDMA(hsdram, hdma, dma_handle);
|
|
|
|
/* Deinitialize the stream for new transfer */
|
|
_HAL_DMA_DeInit(&dma_handle);
|
|
|
|
/* Configure the DMA stream */
|
|
_HAL_DMA_Init(&dma_handle);
|
|
|
|
/* NVIC configuration for DMA transfer complete interrupt */
|
|
NVIC_SetPriority(SDRAM_DMAx_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
|
|
}
|