229 lines
9.4 KiB
C
229 lines
9.4 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file common/ARMCMx/mpu.h
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* @brief Cortex-Mx MPU support macros and structures.
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*
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* @addtogroup COMMON_ARMCMx_MPU
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* @{
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*/
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#ifndef MPU_H
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#define MPU_H
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/* Other layers may include another header named mpu_v7m.h which is perfectly
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compatible, doing a check here to avoid name conflicts.*/
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#ifndef MPUV7M_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name MPU registers definitions
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* @{
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*/
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#define MPU_TYPE_SEPARATED (1U << 0U)
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#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U)
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#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U)
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#define MPU_CTRL_ENABLE (1U << 0U)
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#define MPU_CTRL_HFNMIENA (1U << 1U)
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#define MPU_CTRL_PRIVDEFENA (1U << 2U)
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#define MPU_RNR_REGION_MASK (255U << 0U)
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#define MPU_RNR_REGION(n) ((n) << 0U)
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#define MPU_RBAR_REGION_MASK (15U << 0U)
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#define MPU_RBAR_REGION(n) ((n) << 0U)
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#define MPU_RBAR_VALID (1U << 4U)
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#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U
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#define MPU_RBAR_ADDR(n) ((n) << 5U)
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#define MPU_RASR_ENABLE (1U << 0U)
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#define MPU_RASR_SIZE_MASK (31U << 1U)
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#define MPU_RASR_SIZE(n) ((n) << 1U)
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#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U)
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#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U)
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#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U)
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#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U)
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#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U)
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#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U)
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#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U)
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#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U)
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#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U)
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#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U)
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#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U)
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#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U)
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#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U)
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#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U)
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#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U)
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#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U)
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#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U)
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#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U)
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#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U)
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#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U)
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#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U)
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#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U)
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#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U)
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#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U)
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#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U)
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#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U)
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#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U)
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#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U)
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#define MPU_RASR_SRD_MASK (255U << 8U)
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#define MPU_RASR_SRD(n) ((n) << 8U)
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#define MPU_RASR_SRD_ALL (0U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U)
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#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U)
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#define MPU_RASR_ATTR_B (1U << 16U)
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#define MPU_RASR_ATTR_C (1U << 17U)
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#define MPU_RASR_ATTR_S (1U << 18U)
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#define MPU_RASR_ATTR_TEX_MASK (7U << 19U)
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#define MPU_RASR_ATTR_TEX(n) ((n) << 19U)
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#define MPU_RASR_ATTR_AP_MASK (7U << 24U)
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#define MPU_RASR_ATTR_AP(n) ((n) << 24U)
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#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U)
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#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U)
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#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U)
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#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U)
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#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U)
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#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U)
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#define MPU_RASR_ATTR_XN (1U << 28U)
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/** @} */
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/**
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* @name Region attributes
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* @{
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*/
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#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0))
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#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B)
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#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C)
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#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)
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#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1))
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#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)
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#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2))
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/** @} */
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/**
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* @name Region identifiers
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* @{
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*/
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#define MPU_REGION_0 0U
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#define MPU_REGION_1 1U
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#define MPU_REGION_2 2U
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#define MPU_REGION_3 3U
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#define MPU_REGION_4 4U
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#define MPU_REGION_5 5U
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#define MPU_REGION_6 6U
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#define MPU_REGION_7 7U
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Enables the MPU.
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* @note MEMFAULENA is enabled in SCB_SHCSR.
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*
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* @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register,
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* the enable bit is enforced
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*
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* @api
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*/
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#define mpuEnable(ctrl) { \
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MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \
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}
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/**
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* @brief Disables the MPU.
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* @note MEMFAULENA is disabled in SCB_SHCSR.
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*
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* @api
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*/
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#define mpuDisable() { \
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SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \
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MPU->CTRL = 0; \
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}
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/**
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* @brief Configures an MPU region.
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*
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* @param[in] region the region number
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* @param[in] address start address of the region, note, there are alignment
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* constraints
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* @param[in] attribs attributes mask as defined in @p MPU_RASR register
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*
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* @api
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*/
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#define mpuConfigureRegion(region, addr, attribs) { \
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MPU->RNR = ((uint32_t)region); \
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MPU->RBAR = ((uint32_t)addr); \
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MPU->RASR = ((uint32_t)attribs); \
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}
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/**
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* @brief Changes an MPU region base address.
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*
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* @param[in] region the region number
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* @param[in] address start address of the region, note, there are alignment
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* constraints
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*
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* @api
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*/
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#define mpuSetRegionAddress(region, addr) { \
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MPU->RNR = ((uint32_t)region); \
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MPU->RBAR = ((uint32_t)addr); \
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}
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* MPUV7M_H */
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#endif /* MPU_H */
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/** @} */
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