441 lines
14 KiB
C
441 lines
14 KiB
C
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/**
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******************************************************************************
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* @file Templates/system_stm32f7xx.c
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* @author MCD Application Team
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* @version V1.0.3
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* @date 22-April-2016
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* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f7xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f7xx_system
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* @{
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*/
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/** @addtogroup STM32F7xx_System_Private_Includes
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* @{
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*/
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#include "stm32f7xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SDRAM mounted
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on DK as data memory */
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/* #define DATA_IN_ExtSDRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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gU32 SystemCoreClock = 16000000;
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const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (DATA_IN_ExtSDRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (gU32)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (gU32)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (gU32)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#if defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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SystemCoreClock = pllvco/pllp;
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK frequency --------------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK frequency */
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SystemCoreClock >>= tmp;
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}
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#if defined (DATA_IN_ExtSDRAM)
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f7xx.s before jump to main.
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* This function configures the external memories (SDRAM)
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* This SDRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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register gU32 tmpreg = 0, timeout = 0xFFFF;
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register __IO gU32 index;
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/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface
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clock */
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RCC->AHB1ENR |= 0x000000FC;
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/* Connect PCx pins to FMC Alternate function */
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GPIOC->AFR[0] = 0x0000C000;
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GPIOC->AFR[1] = 0x00000000;
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/* Configure PCx pins in Alternate function mode */
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GPIOC->MODER = 0x00000080;
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/* Configure PCx pins speed to 50 MHz */
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GPIOC->OSPEEDR = 0x00000080;
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/* Configure PCx pins Output type to push-pull */
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GPIOC->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PCx pins */
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GPIOC->PUPDR = 0x00000040;
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x000000CC;
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GPIOD->AFR[1] = 0xCC000CCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xA02A000A;
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/* Configure PDx pins speed to 50 MHz */
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GPIOD->OSPEEDR = 0xA02A000A;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x50150005;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00000CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA800A;
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/* Configure PEx pins speed to 50 MHz */
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GPIOE->OSPEEDR = 0xAAAA800A;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x55554005;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCCC000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA800AAA;
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/* Configure PFx pins speed to 50 MHz */
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GPIOF->OSPEEDR = 0xAA800AAA;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x55400555;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0x00CC00CC;
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GPIOG->AFR[1] = 0xC000000C;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0x80020A0A;
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/* Configure PGx pins speed to 50 MHz */
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GPIOG->OSPEEDR = 0x80020A0A;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
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GPIOG->PUPDR = 0x40010505;
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/* Connect PHx pins to FMC Alternate function */
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GPIOH->AFR[0] = 0x00C0C000;
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GPIOH->AFR[1] = 0x00000000;
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/* Configure PHx pins in Alternate function mode */
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GPIOH->MODER = 0x00000880;
|
||
|
|
/* Configure PHx pins speed to 50 MHz */
|
||
|
|
GPIOH->OSPEEDR = 0x00000880;
|
||
|
|
/* Configure PHx pins Output type to push-pull */
|
||
|
|
GPIOH->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PHx pins */
|
||
|
|
GPIOH->PUPDR = 0x00000440;
|
||
|
|
|
||
|
|
/* Enable the FMC interface clock */
|
||
|
|
RCC->AHB3ENR |= 0x00000001;
|
||
|
|
|
||
|
|
/* Configure and enable SDRAM bank1 */
|
||
|
|
FMC_Bank5_6->SDCR[0] = 0x00001954;
|
||
|
|
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||
|
|
|
||
|
|
/* SDRAM initialization sequence */
|
||
|
|
/* Clock enable command */
|
||
|
|
FMC_Bank5_6->SDCMR = 0x00000011;
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Delay */
|
||
|
|
for (index = 0; index<1000; index++);
|
||
|
|
|
||
|
|
/* PALL command */
|
||
|
|
FMC_Bank5_6->SDCMR = 0x00000012;
|
||
|
|
timeout = 0xFFFF;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Auto refresh command */
|
||
|
|
FMC_Bank5_6->SDCMR = 0x000000F3;
|
||
|
|
timeout = 0xFFFF;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* MRD register program */
|
||
|
|
FMC_Bank5_6->SDCMR = 0x00044014;
|
||
|
|
timeout = 0xFFFF;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set refresh count */
|
||
|
|
tmpreg = FMC_Bank5_6->SDRTR;
|
||
|
|
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
|
||
|
|
|
||
|
|
/* Disable write protection */
|
||
|
|
tmpreg = FMC_Bank5_6->SDCR[0];
|
||
|
|
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Disable the FMC bank1 (enabled after reset).
|
||
|
|
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
|
||
|
|
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
|
||
|
|
*/
|
||
|
|
FMC_Bank1->BTCR[0] = 0x000030d2;
|
||
|
|
}
|
||
|
|
#endif /* DATA_IN_ExtSDRAM */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|