463 lines
15 KiB
C
463 lines
15 KiB
C
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/**
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******************************************************************************
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* @file stm324x9i_eval_sdram.c
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* @author MCD Application Team
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* @version V2.2.3
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* @date 22-April-2016
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* @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
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* device mounted on STM324x9I-EVAL evaluation board.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* File Info : -----------------------------------------------------------------
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User NOTES
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1. How To use this driver:
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--------------------------
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- This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
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on STM324x9I-EVAL evaluation board.
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- This driver does not need a specific component driver for the SDRAM device
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to be included with.
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2. Driver description:
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---------------------
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+ Initialization steps:
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o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
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function includes the MSP layer hardware resources initialization and the
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FMC controller configuration to interface with the external SDRAM memory.
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o It contains the SDRAM initialization sequence to program the SDRAM external
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device using the function BSP_SDRAM_Initialization_sequence(). Note that this
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sequence is standard for all SDRAM devices, but can include some differences
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from a device to another. If it is the case, the right sequence should be
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implemented separately.
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+ SDRAM read/write operations
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o SDRAM external memory can be accessed with read/write operations once it is
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initialized.
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Read/write operation can be performed with AHB access using the functions
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BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
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BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
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o The AHB access is performed with 32-bit width transaction, the DMA transfer
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configuration is fixed at single (no burst) word transfer (see the
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SDRAM_MspInit() static function).
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o User can implement his own functions for read/write access with his desired
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configurations.
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o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
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is called in IRQ handler file, to serve the generated interrupt once the DMA
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transfer is complete.
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o You can send a command to the SDRAM device in runtime using the function
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BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
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the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
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------------------------------------------------------------------------------*/
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/* Includes ------------------------------------------------------------------*/
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#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
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#undef Red
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#undef Green
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#undef Blue
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#endif
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#include "stm324x9i_eval_sdram.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM324x9I_EVAL
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* @{
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM STM324x9I EVAL SDRAM
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* @{
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM_Private_Types_Definitions STM324x9I EVAL SDRAM Private Types Definitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM_Private_Defines STM324x9I EVAL SDRAM Private Defines
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM_Private_Macros STM324x9I EVAL SDRAM Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM_Private_Variables STM324x9I EVAL SDRAM Private Variables
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* @{
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*/
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static SDRAM_HandleTypeDef sdramHandle;
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static FMC_SDRAM_TimingTypeDef Timing;
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static FMC_SDRAM_CommandTypeDef Command;
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/**
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* @}
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM_Private_Function_Prototypes STM324x9I EVAL SDRAM Private Function Prototypes
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* @{
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*/
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static void SDRAM_MspInit(void);
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/**
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* @}
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*/
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/** @defgroup STM324x9I_EVAL_SDRAM_Private_Functions STM324x9I EVAL SDRAM Private Functions
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* @{
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*/
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/**
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* @brief Initializes the SDRAM device.
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* @retval SDRAM status
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*/
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gU8 BSP_SDRAM_Init(void)
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{
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static gU8 sdramstatus = SDRAM_ERROR;
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/* SDRAM device configuration */
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sdramHandle.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 90Mhz as SD clock frequency (System clock is up to 180Mhz */
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Timing.LoadToActiveDelay = 2;
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Timing.ExitSelfRefreshDelay = 7;
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Timing.SelfRefreshTime = 4;
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Timing.RowCycleDelay = 7;
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Timing.WriteRecoveryTime = 2;
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Timing.RPDelay = 2;
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Timing.RCDDelay = 2;
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sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
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sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
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sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
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sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
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sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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/* SDRAM controller initialization */
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SDRAM_MspInit();
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if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
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{
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sdramstatus = SDRAM_ERROR;
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}
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else
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{
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sdramstatus = SDRAM_OK;
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}
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/* SDRAM initialization sequence */
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BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
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return sdramstatus;
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}
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/**
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* @brief Programs the SDRAM device.
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* @param RefreshCount: SDRAM refresh counter value
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*/
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void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount)
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{
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__IO gU32 tmpmrd = 0;
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/* Step 1: Configure a clock configuration enable command */
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Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 2: Insert 100 us minimum delay */
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/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
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HAL_Delay(1);
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/* Step 3: Configure a PALL (precharge all) command */
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Command.CommandMode = FMC_SDRAM_CMD_PALL;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 4: Configure an Auto Refresh command */
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Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 8;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 5: Program the external memory mode register */
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tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
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SDRAM_MODEREG_CAS_LATENCY_3 |\
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 6: Set the refresh rate counter */
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/* Set the device refresh rate */
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HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
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}
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/**
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* @brief Reads an mount of data from the SDRAM memory in polling mode.
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* @param uwStartAddress: Read start address
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* @param pData: Pointer to data to be read
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* @param uwDataSize: Size of read data from the memory
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* @retval SDRAM status
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*/
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gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
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{
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if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
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{
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return SDRAM_ERROR;
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}
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else
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{
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return SDRAM_OK;
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}
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}
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/**
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* @brief Reads an mount of data from the SDRAM memory in DMA mode.
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* @param uwStartAddress: Read start address
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* @param pData: Pointer to data to be read
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* @param uwDataSize: Size of read data from the memory
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* @retval SDRAM status
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*/
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gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
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{
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if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
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{
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return SDRAM_ERROR;
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}
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else
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{
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return SDRAM_OK;
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}
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}
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/**
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* @brief Writes an mount of data to the SDRAM memory in polling mode.
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* @param uwStartAddress: Write start address
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* @param pData: Pointer to data to be written
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* @param uwDataSize: Size of written data from the memory
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* @retval SDRAM status
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*/
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gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
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{
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if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
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{
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return SDRAM_ERROR;
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}
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else
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{
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return SDRAM_OK;
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}
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}
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/**
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* @brief Writes an mount of data to the SDRAM memory in DMA mode.
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* @param uwStartAddress: Write start address
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* @param pData: Pointer to data to be written
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* @param uwDataSize: Size of written data from the memory
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* @retval SDRAM status
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*/
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gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
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{
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if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
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{
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return SDRAM_ERROR;
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}
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else
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{
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return SDRAM_OK;
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}
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}
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/**
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* @brief Sends command to the SDRAM bank.
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* @param SdramCmd: Pointer to SDRAM command structure
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* @retval HAL status
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*/
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gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
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{
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if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
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{
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return SDRAM_ERROR;
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}
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else
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{
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return SDRAM_OK;
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}
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}
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/**
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* @brief Handles SDRAM DMA transfer interrupt request.
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*/
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void BSP_SDRAM_DMA_IRQHandler(void)
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{
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HAL_DMA_IRQHandler(sdramHandle.hdma);
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}
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/**
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* @brief Initializes SDRAM MSP.
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*/
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static void SDRAM_MspInit(void)
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{
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static DMA_HandleTypeDef dmaHandle;
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GPIO_InitTypeDef GPIO_Init_Structure;
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SDRAM_HandleTypeDef *hsdram = &sdramHandle;
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/* Enable FMC clock */
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__FMC_CLK_ENABLE();
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|
|
||
|
|
/* Enable chosen DMAx clock */
|
||
|
|
__DMAx_CLK_ENABLE();
|
||
|
|
|
||
|
|
/* Enable GPIOs clock */
|
||
|
|
__GPIOD_CLK_ENABLE();
|
||
|
|
__GPIOE_CLK_ENABLE();
|
||
|
|
__GPIOF_CLK_ENABLE();
|
||
|
|
__GPIOG_CLK_ENABLE();
|
||
|
|
__GPIOH_CLK_ENABLE();
|
||
|
|
__GPIOI_CLK_ENABLE();
|
||
|
|
|
||
|
|
/* Common GPIO configuration */
|
||
|
|
GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
|
||
|
|
GPIO_Init_Structure.Pull = GPIO_PULLUP;
|
||
|
|
GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
|
||
|
|
GPIO_Init_Structure.Alternate = GPIO_AF12_FMC;
|
||
|
|
|
||
|
|
/* GPIOD configuration */
|
||
|
|
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
|
||
|
|
GPIO_PIN_14 | GPIO_PIN_15;
|
||
|
|
|
||
|
|
|
||
|
|
HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure);
|
||
|
|
|
||
|
|
/* GPIOE configuration */
|
||
|
|
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
|
||
|
|
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||
|
|
GPIO_PIN_15;
|
||
|
|
|
||
|
|
HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure);
|
||
|
|
|
||
|
|
/* GPIOF configuration */
|
||
|
|
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
|
||
|
|
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||
|
|
GPIO_PIN_15;
|
||
|
|
|
||
|
|
HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure);
|
||
|
|
|
||
|
|
/* GPIOG configuration */
|
||
|
|
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
|
||
|
|
GPIO_PIN_15;
|
||
|
|
HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure);
|
||
|
|
|
||
|
|
/* GPIOH configuration */
|
||
|
|
GPIO_Init_Structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\
|
||
|
|
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||
|
|
GPIO_PIN_15;
|
||
|
|
HAL_GPIO_Init(GPIOH, &GPIO_Init_Structure);
|
||
|
|
|
||
|
|
/* GPIOI configuration */
|
||
|
|
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
|
||
|
|
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
|
||
|
|
HAL_GPIO_Init(GPIOI, &GPIO_Init_Structure);
|
||
|
|
|
||
|
|
/* Configure common DMA parameters */
|
||
|
|
dmaHandle.Init.Channel = SDRAM_DMAx_CHANNEL;
|
||
|
|
dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;
|
||
|
|
dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;
|
||
|
|
dmaHandle.Init.MemInc = DMA_MINC_ENABLE;
|
||
|
|
dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||
|
|
dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||
|
|
dmaHandle.Init.Mode = DMA_NORMAL;
|
||
|
|
dmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
|
||
|
|
dmaHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||
|
|
dmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||
|
|
dmaHandle.Init.MemBurst = DMA_MBURST_SINGLE;
|
||
|
|
dmaHandle.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||
|
|
|
||
|
|
dmaHandle.Instance = SDRAM_DMAx_STREAM;
|
||
|
|
|
||
|
|
/* Associate the DMA handle */
|
||
|
|
__HAL_LINKDMA(hsdram, hdma, dmaHandle);
|
||
|
|
|
||
|
|
/* Deinitialize the stream for new transfer */
|
||
|
|
HAL_DMA_DeInit(&dmaHandle);
|
||
|
|
|
||
|
|
/* Configure the DMA stream */
|
||
|
|
HAL_DMA_Init(&dmaHandle);
|
||
|
|
|
||
|
|
/* NVIC configuration for DMA transfer complete interrupt */
|
||
|
|
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
|
||
|
|
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|