109 lines
4.2 KiB
ArmAsm
109 lines
4.2 KiB
ArmAsm
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SAMA5D2/boot.S
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* @brief SAMA5D2 boot-related code managing the trusted zone.
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*
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* @addtogroup SAMA5D2_BOOT
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* @{
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*/
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#if !defined(__DOXYGEN__)
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.set SCR_NS, 0x01
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.set SCR_IRQ, 0x02
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.set SCR_FIQ, 0x04
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.set SCR_EA, 0x08
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.set SCR_FW, 0x10
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.set SCR_AW, 0x20
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.set AIC_REDIR_KEY, 0x5B6C0E26 << 1
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.set SFR_SN1, 0xF8030050
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.set SFR_AICREDIR, 0xF8030054
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.set SFR_L2CC_HRAMC, 0xF8030058
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.set L2CC_CR, 0x00A00100
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.set SCR_RESET_VAL, (SCR_EA|SCR_IRQ)
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.section .boot
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.code 32
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.balign 4
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/*
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* Boot initialization code
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*/
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.global Boot_Handler
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Boot_Handler:
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/*
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* Set VBAR to system vectors table
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* Set MVBAR to monitor vectors table
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*/
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ldr r0, =_start
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mcr p15, 0, r0, c12, c0, 0
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ldr r0, =_monitor_vectors
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mcr p15, 0, r0, c12, c0, 1
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/*
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* Do not redirect secure interrupts to AIC
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*/
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ldr r0, =AIC_REDIR_KEY
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ldr r1, =SFR_SN1
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ldr r1, [r1]
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eor r0, r0, r1
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bic r0, r0, #0x1
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ldr r1, =SFR_AICREDIR
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str r0, [r1]
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#if defined(ARM_RESET_SYS_CTRL)
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/*
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* Reset SCTLR Settings
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*/
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mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register
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bic r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
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bic r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
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bic r0, r0, #0x1 // Clear M bit 0 to disable MMU
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bic r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
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bic r0, r0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
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mcr p15, 0, r0, c1, c0, 0 // Write value back to CP15 System Control register
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isb
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/*
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* Turn off L2Cache
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*/
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bic r0, r0, #0x1
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ldr r1, =L2CC_CR
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str r0, [r1]
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/*
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* Configure the L2 cache to be used as an internal SRAM
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*/
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bic r0, r0, #0x1
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ldr r1, =SFR_L2CC_HRAMC
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str r0, [r1]
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#endif
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/*
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* Enabling Cycle counter
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*/
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mrc p15, 0, r0, c9, c12, 0 // read PMCR register
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orr r0, r0, #(0x1) // set E bit 0 to enable counter
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mcr p15, 0, r0, c9, c12, 0 // write r0
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mrc p15, 0, r0, c9, c12, 1 // read PMCNTENSET register
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orr r0, r0, #(0x1 << 31) // set bit 31 to enable counter
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mcr p15, 0, r0, c9, c12, 1 // write r0
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/*
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* Configure the intial catching of the interrupts
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*/
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ldr r0, =SCR_RESET_VAL // IRQ and external ABT to monitor in secure mode
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mcr p15, 0, r0, c1, c1, 0
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b Reset_Handler
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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