82 lines
3.3 KiB
C
82 lines
3.3 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef _MCUCONF_H_
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#define _MCUCONF_H_
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#define K20x_MCUCONF
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/*
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* HAL driver system settings.
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*/
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/* Select the MCU clocking mode below by enabling the appropriate block. */
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/* Enable clock initialization by HAL */
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#define KINETIS_NO_INIT FALSE
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/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
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#if 1
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
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#define KINETIS_PLLCLK_FREQUENCY 96000000UL
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#define KINETIS_SYSCLK_FREQUENCY 48000000UL
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#endif
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/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */
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#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */
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#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
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#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
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#endif /* 0 */
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/* FEE mode - 24 MHz with external 32.768 kHz crystal */
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/* not implemented */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
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#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
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#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
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#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
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#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
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#endif /* 0 */
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/* FEE mode - 48 MHz */
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/* not implemented */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#endif /* 0 */
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/*
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* SERIAL driver system settings.
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*/
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#define KINETIS_SERIAL_USE_UART0 TRUE
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#endif /* _MCUCONF_H_ */
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