161 lines
6.8 KiB
C
161 lines
6.8 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file common/ARMCMx/cache.h
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* @brief Cortex-Mx cache support macros and structures.
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*
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* @addtogroup COMMON_ARMCMx_CACHE
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* @{
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*/
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#ifndef CACHE_H
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#define CACHE_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#if defined(__DCACHE_PRESENT) || defined(__DOXYGEN__)
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/**
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* @brief Data cache line size, zero if there is no data cache.
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*/
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#define CACHE_LINE_SIZE 32U
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#else
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#define CACHE_LINE_SIZE 0U
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#endif
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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#if defined(__DCACHE_PRESENT) || defined(__DOXYGEN__)
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#if (__DCACHE_PRESENT != 0) || defined(__DOXYGEN__)
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/**
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* @brief Aligns the specified size to a multiple of cache line size.
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* @note This macros assumes that the size of the type @p t is a power of
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* two and not greater than @p CACHE_LINE_SIZE.
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*
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* @param[in] t type of the buffer element
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* @param[in] n number of buffer elements
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*/
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#define CACHE_SIZE_ALIGN(t, n) \
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((((((n) * sizeof (t)) - 1U) | (CACHE_LINE_SIZE - 1U)) + 1U) / sizeof (t))
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/**
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* @brief Invalidates the data cache lines overlapping a memory buffer.
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* @details This function is meant to make sure that data written in
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* data cache is invalidated.
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* @note On devices without data cache this function does nothing.
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* @note The function does not consider the lower 5 bits of addresses,
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* the buffers are meant to be aligned to a 32 bytes boundary or
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* adjacent data can be invalidated as side effect.
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*
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* @param[in] saddr start address of the DMA buffer
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* @param[in] n size of the DMA buffer in bytes
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*
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* @api
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*/
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#define cacheBufferInvalidate(saddr, n) { \
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uint8_t *start = (uint8_t *)(saddr); \
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uint8_t *end = start + (size_t)(n); \
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__DSB(); \
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while (start < end) { \
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SCB->DCIMVAC = (uint32_t)start; \
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start += CACHE_LINE_SIZE; \
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} \
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__DSB(); \
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__ISB(); \
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}
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/**
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* @brief Flushes the data cache lines overlapping a DMA buffer.
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* @details This function is meant to make sure that data written in
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* data cache is flushed to RAM.
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* @note On devices without data cache this function does nothing.
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* @note The function does not consider the lower 5 bits of addresses,
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* the buffers are meant to be aligned to a 32 bytes boundary or
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* adjacent data can be flushed as side effect.
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*
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* @param[in] saddr start address of the DMA buffer
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* @param[in] n size of the DMA buffer in bytes
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*
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* @api
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*/
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#define cacheBufferFlush(saddr, n) { \
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uint8_t *start = (uint8_t *)(saddr); \
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uint8_t *end = start + (size_t)(n); \
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__DSB(); \
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while (start < end) { \
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SCB->DCCIMVAC = (uint32_t)start; \
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start += CACHE_LINE_SIZE; \
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} \
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__DSB(); \
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__ISB(); \
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}
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#else /* __DCACHE_PRESENT == 0 */
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#define cacheBufferInvalidate(addr, size) { \
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(void)(addr); \
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(void)(size); \
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}
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#define cacheBufferFlush(addr, size) { \
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(void)(addr); \
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(void)(size); \
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}
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#endif
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#else /* !defined(__DCACHE_PRESENT) */
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#define CACHE_SIZE_ALIGN(t, n) (n)
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#define cacheBufferInvalidate(addr, size) { \
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(void)(addr); \
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(void)(size); \
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}
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#define cacheBufferFlush(addr, size) { \
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(void)(addr); \
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(void)(size); \
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}
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#endif
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CACHE_H */
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/** @} */
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