80 lines
2.8 KiB
C
80 lines
2.8 KiB
C
/*
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ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef _MCUCONF_H_
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#define _MCUCONF_H_
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#define KL2x_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#if 1
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/* High-frequency internal RC, 48MHz, possible USB clock recovery */
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#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
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#define KINETIS_SYSCLK_FREQUENCY 48000000UL
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#define KINETIS_CLKDIV1_OUTDIV1 1
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#endif
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#if 0
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/* Low-frequency internal RC, 8 MHz mode */
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#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_LIRC8M
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#define KINETIS_SYSCLK_FREQUENCY 8000000UL
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#define KINETIS_CLKDIV1_OUTDIV1 1
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#endif
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/*
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* SERIAL driver system settings.
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*/
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#define KINETIS_SERIAL_USE_UART0 TRUE
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/*
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* USB driver settings
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*/
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#define KINETIS_USB_USE_USB0 TRUE
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/* need to redefine this, since the default is for K20x */
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#define KINETIS_USB_USB0_IRQ_PRIORITY 2
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/*
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* Kinetis FOPT configuration byte
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*/
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/* for KL27: */
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// #define KINETIS_NV_FOPT_BYTE 0x3D
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/* NV_FOPT: bit7-6/BOOTSRC_SEL=0b00 (11=from ROM; 00=from FLASH)
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bit5/FAST_INIT=1, bit4/LPBOOT1=1,
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bit3/RESET_PIN_CFG=1, bit2/NMI_DIS=1,
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bit1/BOOTPIN_OPT=0, bit0/LPBOOT0=1 */
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/* BOOTPIN_OPT: 1=boot depends on BOOTSRC_SEL
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0=boot samples BOOTCFG0=NMI pin */
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/* Boot sequence, page 88 of manual:
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* - If the NMI/BOOTCFG0 input is high or the NMI function is disabled in FTFA_FOPT, the CPU begins execution at the PC location.
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* - If the NMI/BOOTCFG0 input is low, the NMI function is enabled in FTFA_FOPT, and FTFA_FOPT[BOOTPIN_OPT] = 1, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler.
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* - When FTFA_FOPT[BOOTPIN_OPT] = 0, it forces boot from ROM if NMI/BOOTCFG0 pin set to 0.
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*
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* Observed behaviour:
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* - when BOOTPIN_OPT=0, BOOTSRC_SEL still matters:
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* - if 0b11 (from ROM), it still boots from ROM, even if BOOTCFG0 pin
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* is high/floating, but leaves ROM and runs user app after
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* 5 seconds delay.
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* - if 0b00 (from FLASH), reset/powerup jumps to user app unless
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* BOOTCFG0 pin is asserted.
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* - in any case, reset when in bootloader induces the 5 second delay
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* before starting the user app.
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*
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*/
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#endif /* _MCUCONF_H_ */
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