363 lines
20 KiB
C
363 lines
20 KiB
C
/*
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* Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _K20x7_H_
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#define _K20x7_H_
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/*
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* ==============================================================
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* ---------- Interrupt Number Definition -----------------------
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* ==============================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M0 Processor Exceptions Numbers ****************/
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InitialSP_IRQn = -15,
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InitialPC_IRQn = -15,
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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/****** K20x Specific Interrupt Numbers ***********************/
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DMA0_IRQn = 0, // Vector40
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DMA1_IRQn = 1, // Vector44
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DMA2_IRQn = 2, // Vector48
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DMA3_IRQn = 3, // Vector4C
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DMA4_IRQn = 4, // Vector50
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DMA5_IRQn = 5, // Vector54
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DMA6_IRQn = 6, // Vector58
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DMA7_IRQn = 7, // Vector5C
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DMA8_IRQn = 8, // Vector60
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DMA9_IRQn = 9, // Vector64
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DMA10_IRQn = 10, // Vector68
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DMA11_IRQn = 11, // Vector6C
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DMA12_IRQn = 12, // Vector70
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DMA13_IRQn = 13, // Vector74
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DMA14_IRQn = 14, // Vector78
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DMA15_IRQn = 15, // Vector7C
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DMAError_IRQn = 16, // Vector80
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//~ DMA_IRQn = 17, // Vector84
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FlashMemComplete_IRQn = 18, // Vector88
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FlashMemReadCollision_IRQn = 19, // Vector8C
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LowVoltageWarning_IRQn = 20, // Vector90
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LLWU_IRQn = 21, // Vector94
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WDOG_IRQn = 22, // Vector98
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I2C0_IRQn = 24, // VectorA0
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I2C1_IRQn = 25, // VectorA4
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SPI0_IRQn = 26, // VectorA8
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SPI1_IRQn = 27, // VectorAC
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CANMessage_IRQn = 29, // VectorB4
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CANBusOff = 30, // VectorB8
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CANError = 31, // VectorBC
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CANTxWarning = 32, // VectorC0
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CANRxWarning = 33, // VectorC4
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CANWakeUp = 34, // VectorC8
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I2S0Tx_IRQn = 35, // VectorCC
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I2S1Rx_IRQn = 36, // VectorD0
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UART0LON_IRQn = 44, // VectorF0
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UART0Status_IRQn = 45, // VectorF4
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UART0Error_IRQn = 46, // VectorF8
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UART1Status_IRQn = 47, // VectorFC
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UART1Error_IRQn = 48, // Vector100
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UART2Status_IRQn = 49, // Vector104
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UART2Error_IRQn = 50, // Vector108
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ADC0_IRQn = 57, // Vector124
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ADC1_IRQn = 58, // Vector128
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CMP0_IRQn = 59, // Vector12C
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CMP1_IRQn = 60, // Vector130
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CMP2_IRQn = 61, // Vector134
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FTM0_IRQn = 62, // Vector138
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FTM1_IRQn = 63, // Vector13C
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FTM2_IRQn = 64, // Vector140
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CMT_IRQn = 65, // Vector144
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RTCAlarm_IRQn = 66, // Vector148
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RTCSeconds_IRQn = 67, // Vector14C
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PITChannel0_IRQn = 68, // Vector150
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PITChannel1_IRQn = 69, // Vector154
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PITChannel2_IRQn = 70, // Vector158
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PITChannel3_IRQn = 71, // Vector15C
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PDB_IRQn = 72, // Vector160
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USB_OTG_IRQn = 73, // Vector164
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USBChargerDetect_IRQn = 74, // Vector168
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DAC0_IRQn = 81, // Vector184
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TSI_IRQn = 83, // Vector18C
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MCG_IRQn = 84, // Vector190
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LPTMR0_IRQn = 85, // Vector194
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PINA_IRQn = 87, // Vector19C
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PINB_IRQn = 88, // Vector1A0
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PINC_IRQn = 89, // Vector1A4
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PIND_IRQn = 90, // Vector1A8
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PINE_IRQn = 91, // Vector1AC
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SoftInitInt_IRQn = 94, // Vector1B8
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/**
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* @brief K20x Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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#define __FPU_PRESENT 0
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#define __MPU_PRESENT 0
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#define __NVIC_PRIO_BITS 4
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#define __Vendor_SysTickConfig 0
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#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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#include "k20xx.h"
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typedef struct
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{
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__IO uint32_t SOPT1;
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__IO uint32_t SOPT1CFG;
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uint32_t RESERVED0[1023];
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__IO uint32_t SOPT2;
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uint32_t RESERVED1[1];
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__IO uint32_t SOPT4;
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__IO uint32_t SOPT5;
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uint32_t RESERVED2[1];
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__IO uint32_t SOPT7;
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uint32_t RESERVED3[2];
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__I uint32_t SDID;
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uint32_t RESERVED4[1];
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__IO uint32_t SCGC2;
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__IO uint32_t SCGC3;
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__IO uint32_t SCGC4;
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__IO uint32_t SCGC5;
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__IO uint32_t SCGC6;
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__IO uint32_t SCGC7;
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__IO uint32_t CLKDIV1;
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__IO uint32_t CLKDIV2;
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__I uint32_t FCFG1;
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__I uint32_t FCFG2;
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__I uint32_t UIDH;
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__I uint32_t UIDMH;
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__I uint32_t UIDML;
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__I uint32_t UIDL;
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} SIM_TypeDef;
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/****************************************************************/
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/* Peripheral memory map */
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/****************************************************************/
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#define AXBS_BASE ((uint32_t)0x40004000) //
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#define DMA_BASE ((uint32_t)0x40008000)
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#define FTFL_BASE ((uint32_t)0x40020000)
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#define DMAMUX_BASE ((uint32_t)0x40021000)
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#define FCAN0_BASE ((uint32_t)0x40024000) //
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#define SPI0_BASE ((uint32_t)0x4002C000)
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#define SPI1_BASE ((uint32_t)0x4002D000) //
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#define I2S0_BASE ((uint32_t)0x4002F000) //
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#define USBDCD_BASE ((uint32_t)0x40035000) //
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#define PDB_BASE ((uint32_t)0x40036000) //
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#define PIT_BASE ((uint32_t)0x40037000)
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#define FTM0_BASE ((uint32_t)0x40038000)
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#define FTM1_BASE ((uint32_t)0x40039000)
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#define ADC0_BASE ((uint32_t)0x4003B000)
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#define RTC_BASE ((uint32_t)0x4003D000) //
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#define VBAT_BASE ((uint32_t)0x4003E000)
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#define LPTMR0_BASE ((uint32_t)0x40040000)
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#define SRF_BASE ((uint32_t)0x40041000)
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#define TSI0_BASE ((uint32_t)0x40045000)
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#define SIM_BASE ((uint32_t)0x40047000)
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#define PORTA_BASE ((uint32_t)0x40049000)
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#define PORTB_BASE ((uint32_t)0x4004A000)
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#define PORTC_BASE ((uint32_t)0x4004B000)
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#define PORTD_BASE ((uint32_t)0x4004C000)
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#define PORTE_BASE ((uint32_t)0x4004D000)
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#define WDOG_BASE ((uint32_t)0x40052000)
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#define EWDOG_BASE ((uint32_t)0x40061000) //
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#define CMT_BASE ((uint32_t)0x40062000) //
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#define MCG_BASE ((uint32_t)0x40064000)
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#define OSC0_BASE ((uint32_t)0x40065000)
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#define I2C0_BASE ((uint32_t)0x40066000)
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#define I2C1_BASE ((uint32_t)0x40067000) //
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#define UART0_BASE ((uint32_t)0x4006A000)
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#define UART1_BASE ((uint32_t)0x4006B000)
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#define UART2_BASE ((uint32_t)0x4006C000)
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#define USBOTG_BASE ((uint32_t)0x40072000)
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#define CMP0_BASE ((uint32_t)0x40073000) //
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#define VREF_BASE ((uint32_t)0x40074000) //
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#define LLWU_BASE ((uint32_t)0x4007C000)
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#define PMC_BASE ((uint32_t)0x4007D000)
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#define SMC_BASE ((uint32_t)0x4007E000) //
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#define RCM_BASE ((uint32_t)0x4007F000) //
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#define FTM2_BASE ((uint32_t)0x400B8000) //
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#define ADC1_BASE ((uint32_t)0x400BB000) //
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#define DAC0_BASE ((uint32_t)0x400CC000) //
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#define GPIOA_BASE ((uint32_t)0x400FF000)
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#define GPIOB_BASE ((uint32_t)0x400FF040)
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#define GPIOC_BASE ((uint32_t)0x400FF080)
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#define GPIOD_BASE ((uint32_t)0x400FF0C0)
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#define GPIOE_BASE ((uint32_t)0x400FF100)
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/****************************************************************/
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/* Peripheral declaration */
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/****************************************************************/
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#define DMA ((DMA_TypeDef *) DMA_BASE)
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#define FTFL ((FTFL_TypeDef *) FTFL_BASE)
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#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
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#define PIT ((PIT_TypeDef *) PIT_BASE)
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#define FTM0 ((FTM_TypeDef *) FTM0_BASE)
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#define FTM1 ((FTM_TypeDef *) FTM1_BASE)
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#define FTM2 ((FTM_TypeDef *) FTM2_BASE)
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#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
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#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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#define VBAT ((volatile uint8_t *)VBAT_BASE) /* 32 bytes */
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#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE)
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#define SYSTEM_REGISTER_FILE ((volatile uint8_t *)SRF_BASE) /* 32 bytes */
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#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
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#define SIM ((SIM_TypeDef *) SIM_BASE)
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#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
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#define PMC ((PMC_TypeDef *) PMC_BASE)
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#define PORTA ((PORT_TypeDef *) PORTA_BASE)
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#define PORTB ((PORT_TypeDef *) PORTB_BASE)
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#define PORTC ((PORT_TypeDef *) PORTC_BASE)
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#define PORTD ((PORT_TypeDef *) PORTD_BASE)
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#define PORTE ((PORT_TypeDef *) PORTE_BASE)
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#define WDOG ((WDOG_TypeDef *) WDOG_BASE)
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#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE)
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#define MCG ((MCG_TypeDef *) MCG_BASE)
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#define OSC0 ((OSC_TypeDef *) OSC0_BASE)
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#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
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#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
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#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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#define UART0 ((UART_TypeDef *) UART0_BASE)
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#define UART1 ((UART_TypeDef *) UART1_BASE)
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#define UART2 ((UART_TypeDef *) UART2_BASE)
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#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
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/****************************************************************/
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/* Peripheral Registers Bits Definition */
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/****************************************************************/
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/****************************************************************/
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/* */
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/* System Integration Module (SIM) */
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/* */
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/****************************************************************/
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/********* Bits definition for SIM_SOPT1 register *************/
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#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */
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#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */
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#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */
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#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */
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#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */
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#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */
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#define SIM_SOPT1_RAMSIZE_SHIFT 12
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#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT))
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#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK))
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/******* Bits definition for SIM_SOPT1CFG register ************/
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#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */
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#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */
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#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */
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/******* Bits definition for SIM_SOPT2 register ************/
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#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */
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#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */
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#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000)
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#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800)
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#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
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#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT))
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#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK))
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#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */
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/******* Bits definition for SIM_SCGC2 register ************/
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#define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) /*!< DAC0 Clock Gate Control */
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/******* Bits definition for SIM_SCGC3 register ************/
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#define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) /*!< ADC1 Clock Gate Control */
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#define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) /*!< FTM2 Clock Gate Control */
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/******* Bits definition for SIM_SCGC4 register ************/
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#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */
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#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */
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#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */
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#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */
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#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */
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#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */
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#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */
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#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */
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#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */
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#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */
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/******* Bits definition for SIM_SCGC5 register ************/
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#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */
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#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */
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#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */
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#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */
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#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */
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#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
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#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
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/******* Bits definition for SIM_SCGC6 register ************/
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#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */
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#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */
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#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */
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#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */
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#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */
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#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */
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#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */
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#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */
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#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */
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#define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) /*!< SPI1 Clock Gate Control */
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#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */
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#define SIM_SCGC6_FCAN0 ((uint32_t)0x00000010) /*!< FlexCAN 0 Clock Gate Control */
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#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */
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#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */
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/******* Bits definition for SIM_SCGC6 register ************/
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#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */
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/****** Bits definition for SIM_CLKDIV1 register ***********/
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#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
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#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT))
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#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK))
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#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
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#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT))
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#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK))
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#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
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#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT))
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#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK))
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/****** Bits definition for SIM_CLKDIV2 register ***********/
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#define SIM_CLKDIV2_USBDIV_SHIFT 1
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#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT))
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#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK))
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#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001)
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#endif
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