/** ****************************************************************************** * @file stm32h753xx.h * @author MCD Application Team * @version V1.1.0 * @date 31-August-2017 * @brief CMSIS STM32H753xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32h753xx * @{ */ #ifndef __STM32H753xx_H #define __STM32H753xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32H7XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FMC_IRQn = 48, /*!< FMC global Interrupt */ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ UART7_IRQn = 82, /*!< UART7 global interrupt */ UART8_IRQn = 83, /*!< UART8 global interrupt */ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ LTDC_IRQn = 88, /*!< LTDC global Interrupt */ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */ OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */ OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */ OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */ DMAMUX1_OVR_IRQn = 102, /*! /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ uint32_t RESERVED1; /*!< Reserved, 0x028 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ uint32_t RESERVED3; /*!< Reserved, 0x044 */ uint32_t RESERVED4; /*!< Reserved, 0x048 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ uint32_t RESERVED9; /*!< Reserved, 0x0AC */ __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ } ADC_Common_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ } FDCAN_GlobalTypeDef; /** * @brief TTFD Controller Area Network */ typedef struct { __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ } TTCAN_TypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ } FDCAN_ClockCalibrationUnit_TypeDef; /** * @brief Consumer Electronics Control */ typedef struct { __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ } CRS_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ } DAC_TypeDef; /** * @brief DFSDM module registers */ typedef struct { __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ } DFSDM_Filter_TypeDef; /** * @brief DFSDM channel configuration registers */ typedef struct { __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and short circuit detector register, Address offset: 0x08 */ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ } DFSDM_Channel_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ }DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; typedef struct { __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } BDMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } BDMA_TypeDef; typedef struct { __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ }DMAMUX_Channel_TypeDef; typedef struct { __IO uint32_t CSR; /*!< DMA Channel Status Register */ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ }DMAMUX_ChannelStatus_TypeDef; typedef struct { __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ }DMAMUX_RequestGen_TypeDef; typedef struct { __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ }DMAMUX_RequestGenStatus_TypeDef; /** * @brief MDMA Controller */ typedef struct { __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ }MDMA_TypeDef; typedef struct { __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ uint32_t RESERVED0; /*!< Reserved, 0x68 */ __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ }MDMA_Channel_TypeDef; /** * @brief DMA2D Controller */ typedef struct { __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ } DMA2D_TypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACECR; __IO uint32_t MACPFR; __IO uint32_t MACWTR; __IO uint32_t MACHT0R; __IO uint32_t MACHT1R; uint32_t RESERVED1[14]; __IO uint32_t MACVTR; uint32_t RESERVED2; __IO uint32_t MACVHTR; uint32_t RESERVED3; __IO uint32_t MACVIR; __IO uint32_t MACIVIR; uint32_t RESERVED4[2]; __IO uint32_t MACTFCR; uint32_t RESERVED5[7]; __IO uint32_t MACRFCR; uint32_t RESERVED6[7]; __IO uint32_t MACISR; __IO uint32_t MACIER; __IO uint32_t MACRXTXSR; uint32_t RESERVED7; __IO uint32_t MACPCSR; __IO uint32_t MACRWKPFR; uint32_t RESERVED8[2]; __IO uint32_t MACLCSR; __IO uint32_t MACLTCR; __IO uint32_t MACLETR; __IO uint32_t MAC1USTCR; uint32_t RESERVED9[12]; __IO uint32_t MACVR; __IO uint32_t MACDR; uint32_t RESERVED10; __IO uint32_t MACHWF0R; __IO uint32_t MACHWF1R; __IO uint32_t MACHWF2R; uint32_t RESERVED11[54]; __IO uint32_t MACMDIOAR; __IO uint32_t MACMDIODR; uint32_t RESERVED12[2]; __IO uint32_t MACARPAR; uint32_t RESERVED13[59]; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; uint32_t RESERVED14[248]; __IO uint32_t MMCCR; __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; uint32_t RESERVED15[14]; __IO uint32_t MMCTSCGPR; __IO uint32_t MMCTMCGPR; int32_t RESERVED16[5]; __IO uint32_t MMCTPCGR; uint32_t RESERVED17[10]; __IO uint32_t MMCRCRCEPR; __IO uint32_t MMCRAEPR; uint32_t RESERVED18[10]; __IO uint32_t MMCRUPGR; uint32_t RESERVED19[9]; __IO uint32_t MMCTLPIMSTR; __IO uint32_t MMCTLPITCR; __IO uint32_t MMCRLPIMSTR; __IO uint32_t MMCRLPITCR; uint32_t RESERVED20[65]; __IO uint32_t MACL3L4C0R; __IO uint32_t MACL4A0R; uint32_t RESERVED21[2]; __IO uint32_t MACL3A0R0R; __IO uint32_t MACL3A1R0R; __IO uint32_t MACL3A2R0R; __IO uint32_t MACL3A3R0R; uint32_t RESERVED22[4]; __IO uint32_t MACL3L4C1R; __IO uint32_t MACL4A1R; uint32_t RESERVED23[2]; __IO uint32_t MACL3A0R1R; __IO uint32_t MACL3A1R1R; __IO uint32_t MACL3A2R1R; __IO uint32_t MACL3A3R1R; uint32_t RESERVED24[108]; __IO uint32_t MACTSCR; __IO uint32_t MACSSIR; __IO uint32_t MACSTSR; __IO uint32_t MACSTNR; __IO uint32_t MACSTSUR; __IO uint32_t MACSTNUR; __IO uint32_t MACTSAR; uint32_t RESERVED25; __IO uint32_t MACTSSR; uint32_t RESERVED26[3]; __IO uint32_t MACTTSSNR; __IO uint32_t MACTTSSSR; uint32_t RESERVED27[2]; __IO uint32_t MACACR; uint32_t RESERVED28; __IO uint32_t MACATSNR; __IO uint32_t MACATSSR; __IO uint32_t MACTSIACR; __IO uint32_t MACTSEACR; __IO uint32_t MACTSICNR; __IO uint32_t MACTSECNR; uint32_t RESERVED29[4]; __IO uint32_t MACPPSCR; uint32_t RESERVED30[3]; __IO uint32_t MACPPSTTSR; __IO uint32_t MACPPSTTNR; __IO uint32_t MACPPSIR; __IO uint32_t MACPPSWR; uint32_t RESERVED31[12]; __IO uint32_t MACPOCR; __IO uint32_t MACSPI0R; __IO uint32_t MACSPI1R; __IO uint32_t MACSPI2R; __IO uint32_t MACLMIR; uint32_t RESERVED32[11]; __IO uint32_t MTLOMR; uint32_t RESERVED33[7]; __IO uint32_t MTLISR; uint32_t RESERVED34[55]; __IO uint32_t MTLTQOMR; __IO uint32_t MTLTQUR; __IO uint32_t MTLTQDR; uint32_t RESERVED35[8]; __IO uint32_t MTLQICSR; __IO uint32_t MTLRQOMR; __IO uint32_t MTLRQMPOCR; __IO uint32_t MTLRQDR; uint32_t RESERVED36[177]; __IO uint32_t DMAMR; __IO uint32_t DMASBMR; __IO uint32_t DMAISR; __IO uint32_t DMADSR; uint32_t RESERVED37[60]; __IO uint32_t DMACCR; __IO uint32_t DMACTCR; __IO uint32_t DMACRCR; uint32_t RESERVED38[2]; __IO uint32_t DMACTDLAR; uint32_t RESERVED39; __IO uint32_t DMACRDLAR; __IO uint32_t DMACTDTPR; uint32_t RESERVED40; __IO uint32_t DMACRDTPR; __IO uint32_t DMACTDRLR; __IO uint32_t DMACRDRLR; __IO uint32_t DMACIER; __IO uint32_t DMACRIWTR; __IO uint32_t DMACSFCSR; uint32_t RESERVED41; __IO uint32_t DMACCATDR; uint32_t RESERVED42; __IO uint32_t DMACCARDR; uint32_t RESERVED43; __IO uint32_t DMACCATBR; uint32_t RESERVED44; __IO uint32_t DMACCARBR; __IO uint32_t DMACSR; uint32_t RESERVED45[2]; __IO uint32_t DMACMFCR; }ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, Address offset: 0x0C */ __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x10 */ __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, Address offset: 0x2C */ __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x30 */ __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x34 */ uint32_t RESERVED3; /*!< Reserved, 0x38 */ uint32_t RESERVED4; /*!< Reserved, 0x3C */ __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, Address offset: 0x4C */ __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x50 */ __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x54 */ }EXTI_TypeDef; typedef struct { __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ uint32_t RESERVED1; /*!< Reserved, 0x0C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ }EXTI_Core_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ __IO uint32_t OPTSR_PRG; /*!< Flash Option Status Current Register, Address offset: 0x20 */ __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */ __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ uint32_t RESERVED2; /*!< Reserved, 0x108 */ __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ } FLASH_TypeDef; /** * @brief Flexible Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FMC_Bank1_TypeDef; /** * @brief Flexible Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; /** * @brief Flexible Memory Controller Bank2 */ typedef struct { __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ uint32_t RESERVED0; /*!< Reserved, 0x70 */ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ } FMC_Bank2_TypeDef; /** * @brief Flexible Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ uint32_t RESERVED; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ } FMC_Bank3_TypeDef; /** * @brief Flexible Memory Controller Bank5 and 6 */ typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ } FMC_Bank5_6_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ } OPAMP_TypeDef; /** * @brief System configuration controller */ typedef struct { uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */ __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */ __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */ __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */ __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */ __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; /** * @brief JPEG Codec */ typedef struct { __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ } JPEG_TypeDef; /** * @brief LCD-TFT Display Controller */ typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ } LTDC_TypeDef; /** * @brief LCD-TFT Display layer x Controller */ typedef struct { __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ uint32_t RESERVED0[2]; /*!< Reserved */ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ uint32_t RESERVED1[3]; /*!< Reserved */ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ } LTDC_Layer_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA4 */ __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ uint32_t RESERVED8[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ uint32_t RESERVED9; /*!< Reserved, Address offset: 0xF8 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ uint32_t RESERVED10[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ uint32_t reserved; /*!< Reserved */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ __IO uint32_t TAMPCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief SPDIF-RX Interface */ typedef struct { __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1A */ } SPDIFRX_TypeDef; /** * @brief Secure digital input/output Interface */ typedef struct { __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ } SDMMC_TypeDef; /** * @brief Delay Block DLYB */ typedef struct { __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ } DLYB_TypeDef; /** * @brief HW Semaphore HSEM */ typedef struct { __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ __IO uint32_t IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ __IO uint32_t ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ __IO uint32_t ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ __IO uint32_t MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch*/ __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ } HSEM_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */ __IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */ __IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */ __IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */ __IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ __IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ __IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */ __IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */ __IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */ __IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */ __IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */ } SPI_TypeDef; /** * @brief QUAD Serial Peripheral Interface */ typedef struct { __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ uint16_t RESERVED9; /*!< Reserved, 0x2A */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ uint16_t RESERVED10; /*!< Reserved, 0x32 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ uint16_t RESERVED12; /*!< Reserved, 0x4A */ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ uint16_t RESERVED13; /*!< Reserved, 0x4E */ uint16_t RESERVED14; /*!< Reserved, 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ } TIM_TypeDef; /** * @brief LPTIMIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ uint16_t RESERVED1; /*!< Reserved, 0x20 */ __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ } LPTIM_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ } COMPOPT_TypeDef; typedef struct { __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ } COMP_TypeDef; typedef struct { __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ uint16_t RESERVED2; /*!< Reserved, 0x12 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ uint16_t RESERVED3; /*!< Reserved, 0x1A */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ uint16_t RESERVED4; /*!< Reserved, 0x26 */ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ uint16_t RESERVED5; /*!< Reserved, 0x2A */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief Single Wire Protocol Master Interface SPWMI */ typedef struct { __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ uint32_t RESERVED1; /*!< Reserved, 0x08 */ __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ } SWPMI_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief Crypto Processor */ typedef struct { __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ } CRYP_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ } HASH_TypeDef; /** * @brief HASH_DIGEST */ typedef struct { __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ } HASH_DIGEST_TypeDef; /** * @brief High resolution Timer (HRTIM) */ /* HRTIM master registers definition */ typedef struct { __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ uint32_t RESERVED0; /*!< Reserved, 0x20 */ __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ }HRTIM_Master_TypeDef; /* HRTIM Timer A to E registers definition */ typedef struct { __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ }HRTIM_Timerx_TypeDef; /* HRTIM common register definition */ typedef struct { __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */ __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ }HRTIM_Common_TypeDef; /* HRTIM register definition */ typedef struct { HRTIM_Master_TypeDef sMasterRegs; HRTIM_Timerx_TypeDef sTimerxRegs[5]; uint32_t RESERVED0[32]; HRTIM_Common_TypeDef sCommonRegs; }HRTIM_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @brief MDIOS */ typedef struct { __IO uint32_t CR; __IO uint32_t WRFR; __IO uint32_t CWRFR; __IO uint32_t RDFR; __IO uint32_t CRDFR; __IO uint32_t SR; __IO uint32_t CLRFR; uint32_t RESERVED[57]; __IO uint32_t DINR0; __IO uint32_t DINR1; __IO uint32_t DINR2; __IO uint32_t DINR3; __IO uint32_t DINR4; __IO uint32_t DINR5; __IO uint32_t DINR6; __IO uint32_t DINR7; __IO uint32_t DINR8; __IO uint32_t DINR9; __IO uint32_t DINR10; __IO uint32_t DINR11; __IO uint32_t DINR12; __IO uint32_t DINR13; __IO uint32_t DINR14; __IO uint32_t DINR15; __IO uint32_t DINR16; __IO uint32_t DINR17; __IO uint32_t DINR18; __IO uint32_t DINR19; __IO uint32_t DINR20; __IO uint32_t DINR21; __IO uint32_t DINR22; __IO uint32_t DINR23; __IO uint32_t DINR24; __IO uint32_t DINR25; __IO uint32_t DINR26; __IO uint32_t DINR27; __IO uint32_t DINR28; __IO uint32_t DINR29; __IO uint32_t DINR30; __IO uint32_t DINR31; __IO uint32_t DOUTR0; __IO uint32_t DOUTR1; __IO uint32_t DOUTR2; __IO uint32_t DOUTR3; __IO uint32_t DOUTR4; __IO uint32_t DOUTR5; __IO uint32_t DOUTR6; __IO uint32_t DOUTR7; __IO uint32_t DOUTR8; __IO uint32_t DOUTR9; __IO uint32_t DOUTR10; __IO uint32_t DOUTR11; __IO uint32_t DOUTR12; __IO uint32_t DOUTR13; __IO uint32_t DOUTR14; __IO uint32_t DOUTR15; __IO uint32_t DOUTR16; __IO uint32_t DOUTR17; __IO uint32_t DOUTR18; __IO uint32_t DOUTR19; __IO uint32_t DOUTR20; __IO uint32_t DOUTR21; __IO uint32_t DOUTR22; __IO uint32_t DOUTR23; __IO uint32_t DOUTR24; __IO uint32_t DOUTR25; __IO uint32_t DOUTR26; __IO uint32_t DOUTR27; __IO uint32_t DOUTR28; __IO uint32_t DOUTR29; __IO uint32_t DOUTR30; __IO uint32_t DOUTR31; } MDIOS_TypeDef; /** * @brief USB_OTG_Core_Registers */ typedef struct { __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ uint32_t Reserved30[2]; /*!< Reserved 030h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ __IO uint32_t CID; /*!< User ID Register 03Ch */ __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ __IO uint32_t GHWCFG1; /* User HW config1 044h*/ __IO uint32_t GHWCFG2; /* User HW config2 048h*/ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** * @brief USB_OTG_device_Registers */ typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ __IO uint32_t DCTL; /*!< dev Control Register 804h */ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ uint32_t Reserved0C; /*!< Reserved 80Ch */ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ uint32_t Reserved20; /*!< Reserved 820h */ uint32_t Reserved9; /*!< Reserved 824h */ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } USB_OTG_DeviceTypeDef; /** * @brief USB_OTG_IN_Endpoint-Specific_Register */ typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ } USB_OTG_INEndpointTypeDef; /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ } USB_OTG_OUTEndpointTypeDef; /** * @brief USB_OTG_Host_Mode_Register_Structures */ typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ uint32_t Reserved40C; /*!< Reserved 40Ch */ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } USB_OTG_HostTypeDef; /** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct { __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ uint32_t Reserved[2]; /*!< Reserved */ } USB_OTG_HostChannelTypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define D1_ITCMRAM_BASE ((uint32_t)0x00000000) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ #define D1_ITCMICP_BASE ((uint32_t)0x00100000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ #define D1_DTCMRAM_BASE ((uint32_t)0x20000000) /*!< Base address of : 128KB system data RAM accessible over DTCM */ #define D1_AXIFLASH_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ #define D1_AXIICP_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ #define D1_AXISRAM_BASE ((uint32_t)0x24000000) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */ #define D2_AXISRAM_BASE ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */ #define D2_AHBSRAM_BASE ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */ #define D3_BKPSRAM_BASE ((uint32_t)0x38800000) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ #define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ #define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */ #define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */ #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ /* Legacy define */ #define FLASH_BASE FLASH_BANK1_BASE /*!< Peripheral memory map */ #define D2_APB1PERIPH_BASE PERIPH_BASE #define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) #define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) #define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000) #define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000) #define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000) #define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000) #define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000) /*!< Legacy Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) /*!< D1_AHB1PERIPH peripherals */ #define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000) #define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000) #define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000) #define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000) #define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000) #define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000) #define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000) #define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000) #define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000) /*!< D2_AHB1PERIPH peripherals */ #define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000) #define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400) #define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800) #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000) #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100) #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300) #define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400) #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000) #define ETH_MAC_BASE (ETH_BASE) /*!< USB registers base address */ #define USB1_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) #define USB2_OTG_FS_PERIPH_BASE ((uint32_t )0x40080000) #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) #define USB_OTG_DEVICE_BASE ((uint32_t )0x800) #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) #define USB_OTG_HOST_BASE ((uint32_t )0x400) #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) #define USB_OTG_FIFO_BASE ((uint32_t )0x1000) #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) /*!< D2_AHB2PERIPH peripherals */ #define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000) #define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000) #define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400) #define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710) #define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800) #define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400) #define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800) /*!< D3_AHB1PERIPH peripherals */ #define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000) #define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400) #define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000) #define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400) #define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000) #define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400) #define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800) #define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400) #define RCC_C1_BASE (RCC_BASE + 0x130) #define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800) #define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00) #define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400) #define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800) #define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000) #define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300) #define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400) /*!< D1_APB1PERIPH peripherals */ #define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) #define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000) /*!< D2_APB1PERIPH peripherals */ #define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00) #define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400) #define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800) #define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00) #define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000) #define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400) #define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800) #define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00) #define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000) #define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400) #define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800) #define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00) #define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800) #define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00) #define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00) #define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400) #define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800) #define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00) #define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400) #define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800) #define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000) #define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000) #define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010) #define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400) #define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000) #define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400) #define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800) #define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00) /*!< D2_APB2PERIPH peripherals */ #define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000) #define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400) #define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000) #define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400) #define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000) #define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400) #define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000) #define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400) #define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800) #define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000) #define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) #define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) #define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) #define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400) #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080) #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100) #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180) #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200) #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280) #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380) /*!< D3_APB1PERIPH peripherals */ #define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000) #define EXTI_D1_BASE (EXTI_BASE + 0x0080) #define EXTI_D2_BASE (EXTI_BASE + 0x00C0) #define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400) #define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00) #define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400) #define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00) #define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400) #define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800) #define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00) #define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000) #define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800) #define COMP1_BASE (COMP12_BASE + 0x0C) #define COMP2_BASE (COMP12_BASE + 0x10) #define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00) #define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000) #define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800) #define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) #define BDMA_Channel0_BASE (BDMA_BASE + 0x0008) #define BDMA_Channel1_BASE (BDMA_BASE + 0x001C) #define BDMA_Channel2_BASE (BDMA_BASE + 0x0030) #define BDMA_Channel3_BASE (BDMA_BASE + 0x0044) #define BDMA_Channel4_BASE (BDMA_BASE + 0x0058) #define BDMA_Channel5_BASE (BDMA_BASE + 0x006C) #define BDMA_Channel6_BASE (BDMA_BASE + 0x0080) #define BDMA_Channel7_BASE (BDMA_BASE + 0x0094) #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004) #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008) #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000C) #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010) #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014) #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018) #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001C) #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100) #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104) #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108) #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010C) #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110) #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114) #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118) #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011C) #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080) #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C) #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010) #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014) #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018) #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C) #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020) #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024) #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028) #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C) #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030) #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034) #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038) #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C) #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100) #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104) #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108) #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C) #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110) #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114) #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118) #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011C) #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0x5C001000) #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040) #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080) #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0) #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100) #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140) #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180) #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0) #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200) #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240) #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280) #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0) #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300) #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340) #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380) #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0) #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM13 ((TIM_TypeDef *) TIM13_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SPI5 ((SPI_TypeDef *) SPI5_BASE) #define SPI6 ((SPI_TypeDef *) SPI6_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define I2C4 ((I2C_TypeDef *) I2C4_BASE) #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC1 ((DAC_TypeDef *) DAC1_BASE) #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) #define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) #define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) #define COMP1 ((COMP_TypeDef *) COMP1_BASE) #define COMP2 ((COMP_TypeDef *) COMP2_BASE) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) #define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define SAI2 ((SAI_TypeDef *) SAI2_BASE) #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) #define SAI3 ((SAI_TypeDef *) SAI3_BASE) #define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) #define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) #define SAI4 ((SAI_TypeDef *) SAI4_BASE) #define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) #define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) #define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) #define HASH ((HASH_TypeDef *) HASH_BASE) #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define BDMA ((BDMA_TypeDef *) BDMA_BASE) #define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) #define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) #define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) #define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) #define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) #define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) #define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) #define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) #define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) #define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define JPEG ((JPEG_TypeDef *) JPGDEC_BASE) #define HSEM ((HSEM_TypeDef *) HSEM_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) #define ETH ((ETH_TypeDef *)ETH_BASE) #define MDMA ((MDMA_TypeDef *)MDMA_BASE) #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) #define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) /* Legacy defines */ #define USB_OTG_HS USB1_OTG_HS #define USB_OTG_FS USB2_OTG_FS #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_ISR register ********************/ #define ADC_ISR_ADRD_Pos (0U) #define ADC_ISR_ADRD_Msk (0x1U << ADC_ISR_ADRD_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRD ADC_ISR_ADRD_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_RDY_Pos (0U) #define ADC_IER_RDY_Msk (0x1U << ADC_IER_RDY_Pos) /*!< 0x00000001 */ #define ADC_IER_RDY ADC_IER_RDY_Msk /*!< ADC Ready (ADRDY) interrupt source */ #define ADC_IER_EOSMP_Pos (1U) #define ADC_IER_EOSMP_Msk (0x1U << ADC_IER_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMP ADC_IER_EOSMP_Msk /*!< ADC End of Sampling interrupt source */ #define ADC_IER_EOC_Pos (2U) #define ADC_IER_EOC_Msk (0x1U << ADC_IER_EOC_Pos) /*!< 0x00000004 */ #define ADC_IER_EOC ADC_IER_EOC_Msk /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IER_EOS_Pos (3U) #define ADC_IER_EOS_Msk (0x1U << ADC_IER_EOS_Pos) /*!< 0x00000008 */ #define ADC_IER_EOS ADC_IER_EOS_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ #define ADC_IER_OVR_Pos (4U) #define ADC_IER_OVR_Msk (0x1U << ADC_IER_OVR_Pos) /*!< 0x00000010 */ #define ADC_IER_OVR ADC_IER_OVR_Msk /*!< ADC overrun interrupt source */ #define ADC_IER_JEOC_Pos (5U) #define ADC_IER_JEOC_Msk (0x1U << ADC_IER_JEOC_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOC ADC_IER_JEOC_Msk /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IER_JEOS_Pos (6U) #define ADC_IER_JEOS_Msk (0x1U << ADC_IER_JEOS_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOS ADC_IER_JEOS_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ #define ADC_IER_AWD1_Pos (7U) #define ADC_IER_AWD1_Msk (0x1U << ADC_IER_AWD1_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1 ADC_IER_AWD1_Msk /*!< ADC Analog watchdog 1 interrupt source */ #define ADC_IER_AWD2_Pos (8U) #define ADC_IER_AWD2_Msk (0x1U << ADC_IER_AWD2_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2 ADC_IER_AWD2_Msk /*!< ADC Analog watchdog 2 interrupt source */ #define ADC_IER_AWD3_Pos (9U) #define ADC_IER_AWD3_Msk (0x1U << ADC_IER_AWD3_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3 ADC_IER_AWD3_Msk /*!< ADC Analog watchdog 3 interrupt source */ #define ADC_IER_JQOVF_Pos (10U) #define ADC_IER_JQOVF_Msk (0x1U << ADC_IER_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVF ADC_IER_JQOVF_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Boost Mode */ #define ADC_CR_BOOST_Pos (8U) #define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Stop of injected conversion */ #define ADC_CR_ADCALLIN_Pos (16U) #define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ #define ADC_CR_LINCALRDYW1_Pos (22U) #define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ #define ADC_CR_LINCALRDYW2_Pos (23U) #define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ #define ADC_CR_LINCALRDYW3_Pos (24U) #define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ #define ADC_CR_LINCALRDYW4_Pos (25U) #define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ #define ADC_CR_LINCALRDYW5_Pos (26U) #define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ #define ADC_CR_LINCALRDYW6_Pos (27U) #define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ #define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ /******************** Bit definition for ADC_CFGR register ********************/ #define ADC_CFGR_DMNGT_Pos (0U) #define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ #define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ #define ADC_CFGR_RES_Pos (2U) #define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_EXTSEL_Pos (5U) #define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ #define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ #define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ #define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ #define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ #define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ #define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ #define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ /******************** Bit definition for ADC_CFGR2 register ********************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ #define ADC_CFGR2_RSHIFT2_Pos (12U) #define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ #define ADC_CFGR2_RSHIFT3_Pos (13U) #define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ #define ADC_CFGR2_RSHIFT4_Pos (14U) #define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ #define ADC_CFGR2_OSR_Pos (16U) #define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ #define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ #define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ #define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ #define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ #define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ #define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ #define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ #define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register ********************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP19_Pos (27U) #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register ********************/ #define ADC_PCSEL_PCSEL_Pos (0U) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ #define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ #define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ #define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ #define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ #define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ #define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ #define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ #define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ #define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ #define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ #define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ #define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ #define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ #define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ #define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ #define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ #define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ #define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ #define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ #define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ #define ADC_LTR1_LT1_Pos (0U) #define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ #define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ #define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ #define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ #define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ #define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ #define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ #define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ #define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ #define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ #define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ #define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ #define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ #define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ #define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ #define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ #define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ #define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ #define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ #define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ #define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ #define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ #define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ #define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ #define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ #define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ #define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ #define ADC_HTR1_HT1_Pos (0U) #define ADC_HTR1_HT1_Msk (0x3FFFFFFU << ADC_HTR1_HT1_Pos) /*!< 0x03FFFFFF */ #define ADC_HTR1_HT1 ADC_HTR1_HT1_Msk /*!< ADC Analog watchdog 1 higher threshold */ #define ADC_HTR1_HT1_0 (0x0000001U << ADC_HTR1_HT1_Pos) /*!< 0x00000001 */ #define ADC_HTR1_HT1_1 (0x0000002U << ADC_HTR1_HT1_Pos) /*!< 0x00000002 */ #define ADC_HTR1_HT1_2 (0x0000004U << ADC_HTR1_HT1_Pos) /*!< 0x00000004 */ #define ADC_HTR1_HT1_3 (0x0000008U << ADC_HTR1_HT1_Pos) /*!< 0x00000008 */ #define ADC_HTR1_HT1_4 (0x0000010U << ADC_HTR1_HT1_Pos) /*!< 0x00000010 */ #define ADC_HTR1_HT1_5 (0x0000020U << ADC_HTR1_HT1_Pos) /*!< 0x00000020 */ #define ADC_HTR1_HT1_6 (0x0000040U << ADC_HTR1_HT1_Pos) /*!< 0x00000040 */ #define ADC_HTR1_HT1_7 (0x0000080U << ADC_HTR1_HT1_Pos) /*!< 0x00000080 */ #define ADC_HTR1_HT1_8 (0x0000100U << ADC_HTR1_HT1_Pos) /*!< 0x00000100 */ #define ADC_HTR1_HT1_9 (0x0000200U << ADC_HTR1_HT1_Pos) /*!< 0x00000200 */ #define ADC_HTR1_HT1_10 (0x0000400U << ADC_HTR1_HT1_Pos) /*!< 0x00000400 */ #define ADC_HTR1_HT1_11 (0x0000800U << ADC_HTR1_HT1_Pos) /*!< 0x00000800 */ #define ADC_HTR1_HT1_12 (0x0001000U << ADC_HTR1_HT1_Pos) /*!< 0x00001000 */ #define ADC_HTR1_HT1_13 (0x0002000U << ADC_HTR1_HT1_Pos) /*!< 0x00002000 */ #define ADC_HTR1_HT1_14 (0x0004000U << ADC_HTR1_HT1_Pos) /*!< 0x00004000 */ #define ADC_HTR1_HT1_15 (0x0008000U << ADC_HTR1_HT1_Pos) /*!< 0x00008000 */ #define ADC_HTR1_HT1_16 (0x0010000U << ADC_HTR1_HT1_Pos) /*!< 0x00010000 */ #define ADC_HTR1_HT1_17 (0x0020000U << ADC_HTR1_HT1_Pos) /*!< 0x00020000 */ #define ADC_HTR1_HT1_18 (0x0040000U << ADC_HTR1_HT1_Pos) /*!< 0x00040000 */ #define ADC_HTR1_HT1_19 (0x0080000U << ADC_HTR1_HT1_Pos) /*!< 0x00080000 */ #define ADC_HTR1_HT1_20 (0x0100000U << ADC_HTR1_HT1_Pos) /*!< 0x00100000 */ #define ADC_HTR1_HT1_21 (0x0200000U << ADC_HTR1_HT1_Pos) /*!< 0x00200000 */ #define ADC_HTR1_HT1_22 (0x0400000U << ADC_HTR1_HT1_Pos) /*!< 0x00400000 */ #define ADC_HTR1_HT1_23 (0x0800000U << ADC_HTR1_HT1_Pos) /*!< 0x00800000 */ #define ADC_HTR1_HT1_24 (0x1000000U << ADC_HTR1_HT1_Pos) /*!< 0x01000000 */ #define ADC_HTR1_HT1_25 (0x2000000U << ADC_HTR1_HT1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2_Pos (0U) #define ADC_LTR2_LT2_Msk (0x3FFFFFFU << ADC_LTR2_LT2_Pos) /*!< 0x03FFFFFF */ #define ADC_LTR2_LT2 ADC_LTR2_LT2_Msk /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 (0x0000001U << ADC_LTR2_LT2_Pos) /*!< 0x00000001 */ #define ADC_LTR2_LT2_1 (0x0000002U << ADC_LTR2_LT2_Pos) /*!< 0x00000002 */ #define ADC_LTR2_LT2_2 (0x0000004U << ADC_LTR2_LT2_Pos) /*!< 0x00000004 */ #define ADC_LTR2_LT2_3 (0x0000008U << ADC_LTR2_LT2_Pos) /*!< 0x00000008 */ #define ADC_LTR2_LT2_4 (0x0000010U << ADC_LTR2_LT2_Pos) /*!< 0x00000010 */ #define ADC_LTR2_LT2_5 (0x0000020U << ADC_LTR2_LT2_Pos) /*!< 0x00000020 */ #define ADC_LTR2_LT2_6 (0x0000040U << ADC_LTR2_LT2_Pos) /*!< 0x00000040 */ #define ADC_LTR2_LT2_7 (0x0000080U << ADC_LTR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_LTR2_LT2_8 (0x0000100U << ADC_LTR2_LT2_Pos) /*!< 0x00000100 */ #define ADC_LTR2_LT2_9 (0x0000200U << ADC_LTR2_LT2_Pos) /*!< 0x00000200 */ #define ADC_LTR2_LT2_10 (0x0000400U << ADC_LTR2_LT2_Pos) /*!< 0x00000400 */ #define ADC_LTR2_LT2_11 (0x0000800U << ADC_LTR2_LT2_Pos) /*!< 0x00000800 */ #define ADC_LTR2_LT2_12 (0x0001000U << ADC_LTR2_LT2_Pos) /*!< 0x00001000 */ #define ADC_LTR2_LT2_13 (0x0002000U << ADC_LTR2_LT2_Pos) /*!< 0x00002000 */ #define ADC_LTR2_LT2_14 (0x0004000U << ADC_LTR2_LT2_Pos) /*!< 0x00004000 */ #define ADC_LTR2_LT2_15 (0x0008000U << ADC_LTR2_LT2_Pos) /*!< 0x00008000 */ #define ADC_LTR2_LT2_16 (0x0010000U << ADC_LTR2_LT2_Pos) /*!< 0x00010000 */ #define ADC_LTR2_LT2_17 (0x0020000U << ADC_LTR2_LT2_Pos) /*!< 0x00020000 */ #define ADC_LTR2_LT2_18 (0x0040000U << ADC_LTR2_LT2_Pos) /*!< 0x00040000 */ #define ADC_LTR2_LT2_19 (0x0080000U << ADC_LTR2_LT2_Pos) /*!< 0x00080000 */ #define ADC_LTR2_LT2_20 (0x0100000U << ADC_LTR2_LT2_Pos) /*!< 0x00100000 */ #define ADC_LTR2_LT2_21 (0x0200000U << ADC_LTR2_LT2_Pos) /*!< 0x00200000 */ #define ADC_LTR2_LT2_22 (0x0400000U << ADC_LTR2_LT2_Pos) /*!< 0x00400000 */ #define ADC_LTR2_LT2_23 (0x0800000U << ADC_LTR2_LT2_Pos) /*!< 0x00800000 */ #define ADC_LTR2_LT2_24 (0x1000000U << ADC_LTR2_LT2_Pos) /*!< 0x01000000 */ #define ADC_LTR2_LT2_25 (0x2000000U << ADC_LTR2_LT2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ #define ADC_HTR2_HT2_Pos (0U) #define ADC_HTR2_HT2_Msk (0x3FFFFFFU << ADC_HTR2_HT2_Pos) /*!< 0x03FFFFFF */ #define ADC_HTR2_HT2 ADC_HTR2_HT2_Msk /*!< ADC Analog watchdog 2 higher threshold */ #define ADC_HTR2_HT2_0 (0x0000001U << ADC_HTR2_HT2_Pos) /*!< 0x00000001 */ #define ADC_HTR2_HT2_1 (0x0000002U << ADC_HTR2_HT2_Pos) /*!< 0x00000002 */ #define ADC_HTR2_HT2_2 (0x0000004U << ADC_HTR2_HT2_Pos) /*!< 0x00000004 */ #define ADC_HTR2_HT2_3 (0x0000008U << ADC_HTR2_HT2_Pos) /*!< 0x00000008 */ #define ADC_HTR2_HT2_4 (0x0000010U << ADC_HTR2_HT2_Pos) /*!< 0x00000010 */ #define ADC_HTR2_HT2_5 (0x0000020U << ADC_HTR2_HT2_Pos) /*!< 0x00000020 */ #define ADC_HTR2_HT2_6 (0x0000040U << ADC_HTR2_HT2_Pos) /*!< 0x00000040 */ #define ADC_HTR2_HT2_7 (0x0000080U << ADC_HTR2_HT2_Pos) /*!< 0x00000080 */ #define ADC_HTR2_HT2_8 (0x0000100U << ADC_HTR2_HT2_Pos) /*!< 0x00000100 */ #define ADC_HTR2_HT2_9 (0x0000200U << ADC_HTR2_HT2_Pos) /*!< 0x00000200 */ #define ADC_HTR2_HT2_10 (0x0000400U << ADC_HTR2_HT2_Pos) /*!< 0x00000400 */ #define ADC_HTR2_HT2_11 (0x0000800U << ADC_HTR2_HT2_Pos) /*!< 0x00000800 */ #define ADC_HTR2_HT2_12 (0x0001000U << ADC_HTR2_HT2_Pos) /*!< 0x00001000 */ #define ADC_HTR2_HT2_13 (0x0002000U << ADC_HTR2_HT2_Pos) /*!< 0x00002000 */ #define ADC_HTR2_HT2_14 (0x0004000U << ADC_HTR2_HT2_Pos) /*!< 0x00004000 */ #define ADC_HTR2_HT2_15 (0x0008000U << ADC_HTR2_HT2_Pos) /*!< 0x00008000 */ #define ADC_HTR2_HT2_16 (0x0010000U << ADC_HTR2_HT2_Pos) /*!< 0x00010000 */ #define ADC_HTR2_HT2_17 (0x0020000U << ADC_HTR2_HT2_Pos) /*!< 0x00020000 */ #define ADC_HTR2_HT2_18 (0x0040000U << ADC_HTR2_HT2_Pos) /*!< 0x00040000 */ #define ADC_HTR2_HT2_19 (0x0080000U << ADC_HTR2_HT2_Pos) /*!< 0x00080000 */ #define ADC_HTR2_HT2_20 (0x0100000U << ADC_HTR2_HT2_Pos) /*!< 0x00100000 */ #define ADC_HTR2_HT2_21 (0x0200000U << ADC_HTR2_HT2_Pos) /*!< 0x00200000 */ #define ADC_HTR2_HT2_22 (0x0400000U << ADC_HTR2_HT2_Pos) /*!< 0x00400000 */ #define ADC_HTR2_HT2_23 (0x0800000U << ADC_HTR2_HT2_Pos) /*!< 0x00800000 */ #define ADC_HTR2_HT2_24 (0x1000000U << ADC_HTR2_HT2_Pos) /*!< 0x01000000 */ #define ADC_HTR2_HT2_25 (0x2000000U << ADC_HTR2_HT2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ #define ADC_LTR3_LT3_Pos (0U) #define ADC_LTR3_LT3_Msk (0x3FFFFFFU << ADC_LTR3_LT3_Pos) /*!< 0x03FFFFFF */ #define ADC_LTR3_LT3 ADC_LTR3_LT3_Msk /*!< ADC Analog watchdog 3 lower threshold */ #define ADC_LTR3_LT3_0 (0x0000001U << ADC_LTR3_LT3_Pos) /*!< 0x00000001 */ #define ADC_LTR3_LT3_1 (0x0000002U << ADC_LTR3_LT3_Pos) /*!< 0x00000002 */ #define ADC_LTR3_LT3_2 (0x0000004U << ADC_LTR3_LT3_Pos) /*!< 0x00000004 */ #define ADC_LTR3_LT3_3 (0x0000008U << ADC_LTR3_LT3_Pos) /*!< 0x00000008 */ #define ADC_LTR3_LT3_4 (0x0000010U << ADC_LTR3_LT3_Pos) /*!< 0x00000010 */ #define ADC_LTR3_LT3_5 (0x0000020U << ADC_LTR3_LT3_Pos) /*!< 0x00000020 */ #define ADC_LTR3_LT3_6 (0x0000040U << ADC_LTR3_LT3_Pos) /*!< 0x00000040 */ #define ADC_LTR3_LT3_7 (0x0000080U << ADC_LTR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_LTR3_LT3_8 (0x0000100U << ADC_LTR3_LT3_Pos) /*!< 0x00000100 */ #define ADC_LTR3_LT3_9 (0x0000200U << ADC_LTR3_LT3_Pos) /*!< 0x00000200 */ #define ADC_LTR3_LT3_10 (0x0000400U << ADC_LTR3_LT3_Pos) /*!< 0x00000400 */ #define ADC_LTR3_LT3_11 (0x0000800U << ADC_LTR3_LT3_Pos) /*!< 0x00000800 */ #define ADC_LTR3_LT3_12 (0x0001000U << ADC_LTR3_LT3_Pos) /*!< 0x00001000 */ #define ADC_LTR3_LT3_13 (0x0002000U << ADC_LTR3_LT3_Pos) /*!< 0x00002000 */ #define ADC_LTR3_LT3_14 (0x0004000U << ADC_LTR3_LT3_Pos) /*!< 0x00004000 */ #define ADC_LTR3_LT3_15 (0x0008000U << ADC_LTR3_LT3_Pos) /*!< 0x00008000 */ #define ADC_LTR3_LT3_16 (0x0010000U << ADC_LTR3_LT3_Pos) /*!< 0x00010000 */ #define ADC_LTR3_LT3_17 (0x0020000U << ADC_LTR3_LT3_Pos) /*!< 0x00020000 */ #define ADC_LTR3_LT3_18 (0x0040000U << ADC_LTR3_LT3_Pos) /*!< 0x00040000 */ #define ADC_LTR3_LT3_19 (0x0080000U << ADC_LTR3_LT3_Pos) /*!< 0x00080000 */ #define ADC_LTR3_LT3_20 (0x0100000U << ADC_LTR3_LT3_Pos) /*!< 0x00100000 */ #define ADC_LTR3_LT3_21 (0x0200000U << ADC_LTR3_LT3_Pos) /*!< 0x00200000 */ #define ADC_LTR3_LT3_22 (0x0400000U << ADC_LTR3_LT3_Pos) /*!< 0x00400000 */ #define ADC_LTR3_LT3_23 (0x0800000U << ADC_LTR3_LT3_Pos) /*!< 0x00800000 */ #define ADC_LTR3_LT3_24 (0x1000000U << ADC_LTR3_LT3_Pos) /*!< 0x01000000 */ #define ADC_LTR3_LT3_25 (0x2000000U << ADC_LTR3_LT3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ #define ADC_HTR3_HT3_Pos (0U) #define ADC_HTR3_HT3_Msk (0x3FFFFFFU << ADC_HTR3_HT3_Pos) /*!< 0x03FFFFFF */ #define ADC_HTR3_HT3 ADC_HTR3_HT3_Msk /*!< ADC Analog watchdog 3 higher threshold */ #define ADC_HTR3_HT3_0 (0x0000001U << ADC_HTR3_HT3_Pos) /*!< 0x00000001 */ #define ADC_HTR3_HT3_1 (0x0000002U << ADC_HTR3_HT3_Pos) /*!< 0x00000002 */ #define ADC_HTR3_HT3_2 (0x0000004U << ADC_HTR3_HT3_Pos) /*!< 0x00000004 */ #define ADC_HTR3_HT3_3 (0x0000008U << ADC_HTR3_HT3_Pos) /*!< 0x00000008 */ #define ADC_HTR3_HT3_4 (0x0000010U << ADC_HTR3_HT3_Pos) /*!< 0x00000010 */ #define ADC_HTR3_HT3_5 (0x0000020U << ADC_HTR3_HT3_Pos) /*!< 0x00000020 */ #define ADC_HTR3_HT3_6 (0x0000040U << ADC_HTR3_HT3_Pos) /*!< 0x00000040 */ #define ADC_HTR3_HT3_7 (0x0000080U << ADC_HTR3_HT3_Pos) /*!< 0x00000080 */ #define ADC_HTR3_HT3_8 (0x0000100U << ADC_HTR3_HT3_Pos) /*!< 0x00000100 */ #define ADC_HTR3_HT3_9 (0x0000200U << ADC_HTR3_HT3_Pos) /*!< 0x00000200 */ #define ADC_HTR3_HT3_10 (0x0000400U << ADC_HTR3_HT3_Pos) /*!< 0x00000400 */ #define ADC_HTR3_HT3_11 (0x0000800U << ADC_HTR3_HT3_Pos) /*!< 0x00000800 */ #define ADC_HTR3_HT3_12 (0x0001000U << ADC_HTR3_HT3_Pos) /*!< 0x00001000 */ #define ADC_HTR3_HT3_13 (0x0002000U << ADC_HTR3_HT3_Pos) /*!< 0x00002000 */ #define ADC_HTR3_HT3_14 (0x0004000U << ADC_HTR3_HT3_Pos) /*!< 0x00004000 */ #define ADC_HTR3_HT3_15 (0x0008000U << ADC_HTR3_HT3_Pos) /*!< 0x00008000 */ #define ADC_HTR3_HT3_16 (0x0010000U << ADC_HTR3_HT3_Pos) /*!< 0x00010000 */ #define ADC_HTR3_HT3_17 (0x0020000U << ADC_HTR3_HT3_Pos) /*!< 0x00020000 */ #define ADC_HTR3_HT3_18 (0x0040000U << ADC_HTR3_HT3_Pos) /*!< 0x00040000 */ #define ADC_HTR3_HT3_19 (0x0080000U << ADC_HTR3_HT3_Pos) /*!< 0x00080000 */ #define ADC_HTR3_HT3_20 (0x0100000U << ADC_HTR3_HT3_Pos) /*!< 0x00100000 */ #define ADC_HTR3_HT3_21 (0x0200000U << ADC_HTR3_HT3_Pos) /*!< 0x00200000 */ #define ADC_HTR3_HT3_22 (0x0400000U << ADC_HTR3_HT3_Pos) /*!< 0x00400000 */ #define ADC_HTR3_HT3_23 (0x0800000U << ADC_HTR3_HT3_Pos) /*!< 0x00800000 */ #define ADC_HTR3_HT3_24 (0x1000000U << ADC_HTR3_HT3_Pos) /*!< 0x01000000 */ #define ADC_HTR3_HT3_25 (0x2000000U << ADC_HTR3_HT3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ********************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ********************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ********************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x00000001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x00000002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ #define ADC_DR_RDATA_2 (0x00000004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ #define ADC_DR_RDATA_3 (0x00000008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ #define ADC_DR_RDATA_4 (0x00000010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ #define ADC_DR_RDATA_5 (0x00000020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ #define ADC_DR_RDATA_6 (0x00000040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ #define ADC_DR_RDATA_7 (0x00000080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ #define ADC_DR_RDATA_8 (0x00000100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ #define ADC_DR_RDATA_9 (0x00000200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ #define ADC_DR_RDATA_10 (0x00000400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ #define ADC_DR_RDATA_11 (0x00000800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ #define ADC_DR_RDATA_12 (0x00001000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ #define ADC_DR_RDATA_13 (0x00002000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ #define ADC_DR_RDATA_14 (0x00004000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ #define ADC_DR_RDATA_15 (0x00008000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ #define ADC_DR_RDATA_16 (0x00010000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ #define ADC_DR_RDATA_17 (0x00020000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ #define ADC_DR_RDATA_18 (0x00040000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ #define ADC_DR_RDATA_19 (0x00080000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ #define ADC_DR_RDATA_20 (0x00100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ #define ADC_DR_RDATA_21 (0x00200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ #define ADC_DR_RDATA_22 (0x00400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ #define ADC_DR_RDATA_23 (0x00800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ #define ADC_DR_RDATA_24 (0x01000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ #define ADC_DR_RDATA_25 (0x02000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ #define ADC_DR_RDATA_26 (0x04000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ #define ADC_DR_RDATA_27 (0x08000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ #define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ #define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ #define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ #define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JSQR register ********************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ #define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ********************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ #define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ #define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ #define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ #define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ #define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ #define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ #define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ #define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ #define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ #define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ #define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ #define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ #define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ #define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ #define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ #define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ #define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ #define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ #define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ #define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ #define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ #define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ #define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ #define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_SSATE_Pos (31U) #define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ /******************** Bit definition for ADC_OFR2 register ********************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ #define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ #define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ #define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ #define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ #define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ #define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ #define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ #define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ #define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ #define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ #define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ #define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ #define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ #define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ #define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ #define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ #define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ #define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ #define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ #define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ #define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ #define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ #define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_SSATE_Pos (31U) #define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ /******************** Bit definition for ADC_OFR3 register ********************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ #define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ #define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ #define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ #define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ #define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ #define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ #define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ #define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ #define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ #define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ #define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ #define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ #define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ #define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ #define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ #define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ #define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ #define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ #define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ #define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ #define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ #define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ #define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_SSATE_Pos (31U) #define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ /******************** Bit definition for ADC_OFR4 register ********************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ #define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ #define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ #define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ #define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ #define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ #define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ #define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ #define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ #define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ #define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ #define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ #define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ #define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ #define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ #define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ #define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ #define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ #define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ #define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ #define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ #define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ #define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ #define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_SSATE_Pos (31U) #define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x00000001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x00000002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR1_JDATA_2 (0x00000004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR1_JDATA_3 (0x00000008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR1_JDATA_4 (0x00000010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR1_JDATA_5 (0x00000020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR1_JDATA_6 (0x00000040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR1_JDATA_7 (0x00000080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR1_JDATA_8 (0x00000100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR1_JDATA_9 (0x00000200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR1_JDATA_10 (0x00000400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR1_JDATA_11 (0x00000800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR1_JDATA_12 (0x00001000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR1_JDATA_13 (0x00002000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR1_JDATA_14 (0x00004000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR1_JDATA_15 (0x00008000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR1_JDATA_16 (0x00010000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR1_JDATA_17 (0x00020000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR1_JDATA_18 (0x00040000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR1_JDATA_19 (0x00080000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR1_JDATA_20 (0x00100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR1_JDATA_21 (0x00200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR1_JDATA_22 (0x00400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR1_JDATA_23 (0x00800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR1_JDATA_24 (0x01000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR1_JDATA_25 (0x02000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR1_JDATA_26 (0x04000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR1_JDATA_27 (0x08000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x00000001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x00000002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR2_JDATA_2 (0x00000004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR2_JDATA_3 (0x00000008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR2_JDATA_4 (0x00000010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR2_JDATA_5 (0x00000020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR2_JDATA_6 (0x00000040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR2_JDATA_7 (0x00000080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR2_JDATA_8 (0x00000100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR2_JDATA_9 (0x00000200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR2_JDATA_10 (0x00000400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR2_JDATA_11 (0x00000800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR2_JDATA_12 (0x00001000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR2_JDATA_13 (0x00002000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR2_JDATA_14 (0x00004000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR2_JDATA_15 (0x00008000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR2_JDATA_16 (0x00010000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR2_JDATA_17 (0x00020000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR2_JDATA_18 (0x00040000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR2_JDATA_19 (0x00080000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR2_JDATA_20 (0x00100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR2_JDATA_21 (0x00200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR2_JDATA_22 (0x00400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR2_JDATA_23 (0x00800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR2_JDATA_24 (0x01000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR2_JDATA_25 (0x02000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR2_JDATA_26 (0x04000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR2_JDATA_27 (0x08000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x00000001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x00000002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR3_JDATA_2 (0x00000004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR3_JDATA_3 (0x00000008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR3_JDATA_4 (0x00000010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR3_JDATA_5 (0x00000020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR3_JDATA_6 (0x00000040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR3_JDATA_7 (0x00000080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR3_JDATA_8 (0x00000100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR3_JDATA_9 (0x00000200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR3_JDATA_10 (0x00000400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR3_JDATA_11 (0x00000800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR3_JDATA_12 (0x00001000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR3_JDATA_13 (0x00002000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR3_JDATA_14 (0x00004000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR3_JDATA_15 (0x00008000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR3_JDATA_16 (0x00010000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR3_JDATA_17 (0x00020000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR3_JDATA_18 (0x00040000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR3_JDATA_19 (0x00080000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR3_JDATA_20 (0x00100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR3_JDATA_21 (0x00200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR3_JDATA_22 (0x00400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR3_JDATA_23 (0x00800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR3_JDATA_24 (0x01000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR3_JDATA_25 (0x02000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR3_JDATA_26 (0x04000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR3_JDATA_27 (0x08000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x00000001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x00000002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR4_JDATA_2 (0x00000004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR4_JDATA_3 (0x00000008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR4_JDATA_4 (0x00000010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR4_JDATA_5 (0x00000020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR4_JDATA_6 (0x00000040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR4_JDATA_7 (0x00000080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR4_JDATA_8 (0x00000100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR4_JDATA_9 (0x00000200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR4_JDATA_10 (0x00000400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR4_JDATA_11 (0x00000800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR4_JDATA_12 (0x00001000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR4_JDATA_13 (0x00002000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR4_JDATA_14 (0x00004000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR4_JDATA_15 (0x00008000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR4_JDATA_16 (0x00010000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR4_JDATA_17 (0x00020000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR4_JDATA_18 (0x00040000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR4_JDATA_19 (0x00080000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR4_JDATA_20 (0x00100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR4_JDATA_21 (0x00200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR4_JDATA_22 (0x00400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR4_JDATA_23 (0x00800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR4_JDATA_24 (0x01000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR4_JDATA_25 (0x02000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR4_JDATA_26 (0x04000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR4_JDATA_27 (0x08000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ********************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ #define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ********************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ #define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ #define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ #define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ #define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ #define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ #define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ #define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ #define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_CALFACT2 register ********************/ #define ADC_CALFACT2_LINCALFACT_Pos (0U) #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ #define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ #define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ #define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ #define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ #define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ #define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ #define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ #define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ #define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ #define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ #define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ #define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ #define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ #define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ #define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ #define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ #define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ #define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ #define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ #define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ #define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ #define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ #define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ #define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ #define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ #define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ #define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ #define ADC_CALFACT2_LINCALFACT_27 (0x08000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ #define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ #define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ #define ADC123_CSR_ADRDY_MST_Pos (0U) #define ADC123_CSR_ADRDY_MST_Msk (0x1U << ADC123_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC123_CSR_ADRDY_MST ADC123_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ #define ADC123_CSR_EOSMP_MST_Pos (1U) #define ADC123_CSR_EOSMP_MST_Msk (0x1U << ADC123_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC123_CSR_EOSMP_MST ADC123_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ #define ADC123_CSR_EOC_MST_Pos (2U) #define ADC123_CSR_EOC_MST_Msk (0x1U << ADC123_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC123_CSR_EOC_MST ADC123_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ #define ADC123_CSR_EOS_MST_Pos (3U) #define ADC123_CSR_EOS_MST_Msk (0x1U << ADC123_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC123_CSR_EOS_MST ADC123_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ #define ADC123_CSR_OVR_MST_Pos (4U) #define ADC123_CSR_OVR_MST_Msk (0x1U << ADC123_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC123_CSR_OVR_MST ADC123_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ #define ADC123_CSR_JEOC_MST_Pos (5U) #define ADC123_CSR_JEOC_MST_Msk (0x1U << ADC123_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC123_CSR_JEOC_MST ADC123_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ #define ADC123_CSR_JEOS_MST_Pos (6U) #define ADC123_CSR_JEOS_MST_Msk (0x1U << ADC123_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC123_CSR_JEOS_MST ADC123_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ #define ADC123_CSR_AWD1_MST_Pos (7U) #define ADC123_CSR_AWD1_MST_Msk (0x1U << ADC123_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC123_CSR_AWD1_MST ADC123_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ #define ADC123_CSR_AWD2_MST_Pos (8U) #define ADC123_CSR_AWD2_MST_Msk (0x1U << ADC123_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC123_CSR_AWD2_MST ADC123_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ #define ADC123_CSR_AWD3_MST_Pos (9U) #define ADC123_CSR_AWD3_MST_Msk (0x1U << ADC123_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC123_CSR_AWD3_MST ADC123_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ #define ADC123_CSR_JQOVF_MST_Pos (10U) #define ADC123_CSR_JQOVF_MST_Msk (0x1U << ADC123_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC123_CSR_JQOVF_MST ADC123_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ #define ADC123_CSR_ADRDY_SLV_Pos (16U) #define ADC123_CSR_ADRDY_SLV_Msk (0x1U << ADC123_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC123_CSR_ADRDY_SLV ADC123_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ #define ADC123_CSR_EOSMP_SLV_Pos (17U) #define ADC123_CSR_EOSMP_SLV_Msk (0x1U << ADC123_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC123_CSR_EOSMP_SLV ADC123_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ #define ADC123_CSR_EOC_SLV_Pos (18U) #define ADC123_CSR_EOC_SLV_Msk (0x1U << ADC123_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC123_CSR_EOC_SLV ADC123_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ #define ADC123_CSR_EOS_SLV_Pos (19U) #define ADC123_CSR_EOS_SLV_Msk (0x1U << ADC123_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC123_CSR_EOS_SLV ADC123_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ #define ADC123_CSR_OVR_SLV_Pos (20U) #define ADC123_CSR_OVR_SLV_Msk (0x1U << ADC123_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC123_CSR_OVR_SLV ADC123_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ #define ADC123_CSR_JEOC_SLV_Pos (21U) #define ADC123_CSR_JEOC_SLV_Msk (0x1U << ADC123_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC123_CSR_JEOC_SLV ADC123_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ #define ADC123_CSR_JEOS_SLV_Pos (22U) #define ADC123_CSR_JEOS_SLV_Msk (0x1U << ADC123_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC123_CSR_JEOS_SLV ADC123_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ #define ADC123_CSR_AWD1_SLV_Pos (23U) #define ADC123_CSR_AWD1_SLV_Msk (0x1U << ADC123_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC123_CSR_AWD1_SLV ADC123_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ #define ADC123_CSR_AWD2_SLV_Pos (24U) #define ADC123_CSR_AWD2_SLV_Msk (0x1U << ADC123_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC123_CSR_AWD2_SLV ADC123_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ #define ADC123_CSR_AWD3_SLV_Pos (25U) #define ADC123_CSR_AWD3_SLV_Msk (0x1U << ADC123_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC123_CSR_AWD3_SLV ADC123_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ #define ADC123_CSR_JQOVF_SLV_Pos (26U) #define ADC123_CSR_JQOVF_SLV_Msk (0x1U << ADC123_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC123_CSR_JQOVF_SLV ADC123_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DAMDF_Pos (14U) #define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ #define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ #define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ #define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ /******************** Bit definition for ADC_CDR register ********************/ #define ADC123_CDR_RDATA_MST_Pos (0U) #define ADC123_CDR_RDATA_MST_Msk (0xFFFFU << ADC123_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC123_CDR_RDATA_MST ADC123_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */ #define ADC123_CDR_RDATA_MST_0 (0x0001U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ #define ADC123_CDR_RDATA_MST_1 (0x0002U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ #define ADC123_CDR_RDATA_MST_2 (0x0004U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ #define ADC123_CDR_RDATA_MST_3 (0x0008U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ #define ADC123_CDR_RDATA_MST_4 (0x0010U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ #define ADC123_CDR_RDATA_MST_5 (0x0020U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ #define ADC123_CDR_RDATA_MST_6 (0x0040U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ #define ADC123_CDR_RDATA_MST_7 (0x0080U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ #define ADC123_CDR_RDATA_MST_8 (0x0100U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ #define ADC123_CDR_RDATA_MST_9 (0x0200U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ #define ADC123_CDR_RDATA_MST_10 (0x0400U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ #define ADC123_CDR_RDATA_MST_11 (0x0800U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ #define ADC123_CDR_RDATA_MST_12 (0x1000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ #define ADC123_CDR_RDATA_MST_13 (0x2000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ #define ADC123_CDR_RDATA_MST_14 (0x4000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ #define ADC123_CDR_RDATA_MST_15 (0x8000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ #define ADC123_CDR_RDATA_SLV_Pos (16U) #define ADC123_CDR_RDATA_SLV_Msk (0xFFFFU << ADC123_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC123_CDR_RDATA_SLV ADC123_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */ #define ADC123_CDR_RDATA_SLV_0 (0x0001U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ #define ADC123_CDR_RDATA_SLV_1 (0x0002U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ #define ADC123_CDR_RDATA_SLV_2 (0x0004U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ #define ADC123_CDR_RDATA_SLV_3 (0x0008U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ #define ADC123_CDR_RDATA_SLV_4 (0x0010U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ #define ADC123_CDR_RDATA_SLV_5 (0x0020U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ #define ADC123_CDR_RDATA_SLV_6 (0x0040U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ #define ADC123_CDR_RDATA_SLV_7 (0x0080U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ #define ADC123_CDR_RDATA_SLV_8 (0x0100U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ #define ADC123_CDR_RDATA_SLV_9 (0x0200U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ #define ADC123_CDR_RDATA_SLV_10 (0x0400U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ #define ADC123_CDR_RDATA_SLV_11 (0x0800U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ #define ADC123_CDR_RDATA_SLV_12 (0x1000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ #define ADC123_CDR_RDATA_SLV_13 (0x2000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ #define ADC123_CDR_RDATA_SLV_14 (0x4000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ #define ADC123_CDR_RDATA_SLV_15 (0x8000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_CDR2 register ********************/ #define ADC123_CDR2_RDATA_ALT_Pos (0U) #define ADC123_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC123_CDR2_RDATA_ALT ADC123_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */ #define ADC123_CDR2_RDATA_ALT_0 (0x00000001U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */ #define ADC123_CDR2_RDATA_ALT_1 (0x00000002U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */ #define ADC123_CDR2_RDATA_ALT_2 (0x00000004U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */ #define ADC123_CDR2_RDATA_ALT_3 (0x00000008U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */ #define ADC123_CDR2_RDATA_ALT_4 (0x00000010U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */ #define ADC123_CDR2_RDATA_ALT_5 (0x00000020U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */ #define ADC123_CDR2_RDATA_ALT_6 (0x00000040U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */ #define ADC123_CDR2_RDATA_ALT_7 (0x00000080U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */ #define ADC123_CDR2_RDATA_ALT_8 (0x00000100U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */ #define ADC123_CDR2_RDATA_ALT_9 (0x00000200U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */ #define ADC123_CDR2_RDATA_ALT_10 (0x00000400U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */ #define ADC123_CDR2_RDATA_ALT_11 (0x00000800U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */ #define ADC123_CDR2_RDATA_ALT_12 (0x00001000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */ #define ADC123_CDR2_RDATA_ALT_13 (0x00002000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */ #define ADC123_CDR2_RDATA_ALT_14 (0x00004000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */ #define ADC123_CDR2_RDATA_ALT_15 (0x00008000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */ #define ADC123_CDR2_RDATA_ALT_16 (0x00010000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */ #define ADC123_CDR2_RDATA_ALT_17 (0x00020000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */ #define ADC123_CDR2_RDATA_ALT_18 (0x00040000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */ #define ADC123_CDR2_RDATA_ALT_19 (0x00080000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */ #define ADC123_CDR2_RDATA_ALT_20 (0x00100000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */ #define ADC123_CDR2_RDATA_ALT_21 (0x00200000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */ #define ADC123_CDR2_RDATA_ALT_22 (0x00400000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */ #define ADC123_CDR2_RDATA_ALT_23 (0x00800000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */ #define ADC123_CDR2_RDATA_ALT_24 (0x01000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */ #define ADC123_CDR2_RDATA_ALT_25 (0x02000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */ #define ADC123_CDR2_RDATA_ALT_26 (0x04000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */ #define ADC123_CDR2_RDATA_ALT_27 (0x08000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */ #define ADC123_CDR2_RDATA_ALT_28 (0x10000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */ #define ADC123_CDR2_RDATA_ALT_29 (0x20000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */ #define ADC123_CDR2_RDATA_ALT_30 (0x40000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC123_CDR2_RDATA_ALT_31 (0x80000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ /* VREFBUF */ /* */ /******************************************************************************/ /******************* Bit definition for VREFBUF_CSR register ****************/ #define VREFBUF_CSR_ENVR_Pos (0U) #define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!> 1) /* 1MB */ #define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __STM32H7xx_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/