701 lines
40 KiB
C
701 lines
40 KiB
C
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//*****************************************************************************
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//
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// hw_timer.h - Defines and macros used when accessing the timer.
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//
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// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_TIMER_H__
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#define __HW_TIMER_H__
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//*****************************************************************************
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//
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// The following are defines for the Timer register offsets.
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//
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//*****************************************************************************
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#define TIMER_O_CFG 0x00000000 // GPTM Configuration
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#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
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#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
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#define TIMER_O_CTL 0x0000000C // GPTM Control
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#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
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#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
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#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
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#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
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#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
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#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
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#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
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#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
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#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
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#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
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#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
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#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
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#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
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#define TIMER_O_TAR 0x00000048 // GPTM Timer A
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#define TIMER_O_TBR 0x0000004C // GPTM Timer B
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#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
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#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
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#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
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#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
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#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
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#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
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#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
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#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
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#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event
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#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
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#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_CFG register.
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//
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//*****************************************************************************
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#define TIMER_CFG_M 0x00000007 // GPTM Configuration
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#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this
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// value selects the 32-bit timer
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// configuration
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#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this
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// value selects the 32-bit
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// real-time clock (RTC) counter
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// configuration
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#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this
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// value selects the 16-bit timer
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// configuration
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_TAMR register.
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//
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//*****************************************************************************
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#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select
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#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations
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#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
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#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
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#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
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#define TIMER_TAMR_TCACT_SETTOGTO \
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0x00008000 // Set CCP immediately and toggle
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// on Time-Out
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#define TIMER_TAMR_TCACT_CLRTOGTO \
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0x0000A000 // Clear CCP immediately and toggle
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// on Time-Out
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#define TIMER_TAMR_TCACT_SETCLRTO \
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0x0000C000 // Set CCP immediately and clear on
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// Time-Out
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#define TIMER_TAMR_TCACT_CLRSETTO \
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0x0000E000 // Clear CCP immediately and set on
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// Time-Out
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#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt
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// Disable
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#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
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// Operation
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#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
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// Update
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#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
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// Enable
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#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
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#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
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#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
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#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
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// Enable
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#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
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#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
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// Select
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#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
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#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
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#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
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#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
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#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_TBMR register.
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//
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//*****************************************************************************
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#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select
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#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations
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#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
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#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
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#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
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#define TIMER_TBMR_TCACT_SETTOGTO \
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0x00008000 // Set CCP immediately and toggle
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// on Time-Out
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#define TIMER_TBMR_TCACT_CLRTOGTO \
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0x0000A000 // Clear CCP immediately and toggle
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// on Time-Out
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#define TIMER_TBMR_TCACT_SETCLRTO \
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0x0000C000 // Set CCP immediately and clear on
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// Time-Out
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#define TIMER_TBMR_TCACT_CLRSETTO \
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0x0000E000 // Clear CCP immediately and set on
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// Time-Out
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#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt
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// Disable
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#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
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// Operation
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#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
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// Update
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#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
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// Enable
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#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
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#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
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#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
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#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
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// Enable
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#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
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#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
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// Select
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#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
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#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
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#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
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#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
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#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_CTL register.
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//
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//*****************************************************************************
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#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
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#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
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// Enable
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#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
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#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
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#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
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#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
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#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
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#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
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#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
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#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
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// Enable
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#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
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#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
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#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
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#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
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#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
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#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
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#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_SYNC register.
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//
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//*****************************************************************************
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#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
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// 5
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#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
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// affected
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#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
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// GPTM 32/64-Bit Timer 5 is
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// triggered
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#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
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// GPTM 32/64-Bit Timer 5 is
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// triggered
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#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
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// and Timer B of GPTM 32/64-Bit
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// Timer 5 is triggered
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#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
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// 4
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#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
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// affected
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#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
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// GPTM 32/64-Bit Timer 4 is
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// triggered
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#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
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// GPTM 32/64-Bit Timer 4 is
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// triggered
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#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
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// and Timer B of GPTM 32/64-Bit
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// Timer 4 is triggered
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#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
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// 3
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#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
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// affected
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#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
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// GPTM 32/64-Bit Timer 3 is
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// triggered
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#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
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// GPTM 32/64-Bit Timer 3 is
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// triggered
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#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
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// and Timer B of GPTM 32/64-Bit
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// Timer 3 is triggered
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#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
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// 2
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#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
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// affected
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#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
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// GPTM 32/64-Bit Timer 2 is
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// triggered
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#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
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// GPTM 32/64-Bit Timer 2 is
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// triggered
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#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
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// and Timer B of GPTM 32/64-Bit
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// Timer 2 is triggered
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#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7
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#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected
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#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of
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// GPTM7 is triggered
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#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of
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// GPTM7 is triggered
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#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A
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// and Timer B of GPTM7 is
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// triggered
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#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
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// 1
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#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
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// affected
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#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
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// GPTM 32/64-Bit Timer 1 is
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// triggered
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#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
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// GPTM 32/64-Bit Timer 1 is
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// triggered
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#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
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// and Timer B of GPTM 32/64-Bit
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// Timer 1 is triggered
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#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
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// 0
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#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
|
||
|
|
// affected
|
||
|
|
#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
|
||
|
|
// GPTM 32/64-Bit Timer 0 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
|
||
|
|
// GPTM 32/64-Bit Timer 0 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM 32/64-Bit
|
||
|
|
// Timer 0 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6
|
||
|
|
#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of
|
||
|
|
// GPTM6 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of
|
||
|
|
// GPTM6 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM6 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5
|
||
|
|
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
|
||
|
|
// GPTM5 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
|
||
|
|
// GPTM5 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM5 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4
|
||
|
|
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
|
||
|
|
// GPTM4 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
|
||
|
|
// GPTM4 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM4 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3
|
||
|
|
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
|
||
|
|
// GPTM3 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
|
||
|
|
// GPTM3 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM3 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2
|
||
|
|
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
|
||
|
|
// GPTM2 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
|
||
|
|
// GPTM2 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM2 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1
|
||
|
|
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
|
||
|
|
// GPTM1 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
|
||
|
|
// GPTM1 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM1 is
|
||
|
|
// triggered
|
||
|
|
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0
|
||
|
|
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected
|
||
|
|
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
|
||
|
|
// GPTM0 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
|
||
|
|
// GPTM0 is triggered
|
||
|
|
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
|
||
|
|
// and Timer B of GPTM0 is
|
||
|
|
// triggered
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_IMR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update
|
||
|
|
// Error Interrupt Mask
|
||
|
|
#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt
|
||
|
|
// Mask
|
||
|
|
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
|
||
|
|
// Mask
|
||
|
|
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
|
||
|
|
// Interrupt Mask
|
||
|
|
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
|
||
|
|
// Interrupt Mask
|
||
|
|
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
|
||
|
|
// Mask
|
||
|
|
#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt
|
||
|
|
// Mask
|
||
|
|
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
|
||
|
|
// Mask
|
||
|
|
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
|
||
|
|
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
|
||
|
|
// Interrupt Mask
|
||
|
|
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
|
||
|
|
// Interrupt Mask
|
||
|
|
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
|
||
|
|
// Mask
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_RIS register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update
|
||
|
|
// Error Raw Interrupt Status
|
||
|
|
#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw
|
||
|
|
// Interrupt Status
|
||
|
|
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
|
||
|
|
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
|
||
|
|
// Raw Interrupt
|
||
|
|
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
|
||
|
|
// Raw Interrupt
|
||
|
|
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
|
||
|
|
// Interrupt
|
||
|
|
#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw
|
||
|
|
// Interrupt Status
|
||
|
|
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
|
||
|
|
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
|
||
|
|
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
|
||
|
|
// Raw Interrupt
|
||
|
|
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
|
||
|
|
// Raw Interrupt
|
||
|
|
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
|
||
|
|
// Interrupt
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_MIS register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update
|
||
|
|
// Error Masked Interrupt Status
|
||
|
|
#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked
|
||
|
|
// Interrupt
|
||
|
|
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
|
||
|
|
// Interrupt
|
||
|
|
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
|
||
|
|
// Masked Interrupt
|
||
|
|
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
|
||
|
|
// Masked Interrupt
|
||
|
|
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
|
||
|
|
// Interrupt
|
||
|
|
#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked
|
||
|
|
// Interrupt
|
||
|
|
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
|
||
|
|
// Interrupt
|
||
|
|
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
|
||
|
|
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
|
||
|
|
// Masked Interrupt
|
||
|
|
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
|
||
|
|
// Masked Interrupt
|
||
|
|
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
|
||
|
|
// Interrupt
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_ICR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update
|
||
|
|
// Error Interrupt Clear
|
||
|
|
#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt
|
||
|
|
// Clear
|
||
|
|
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
|
||
|
|
// Clear
|
||
|
|
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
|
||
|
|
// Interrupt Clear
|
||
|
|
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
|
||
|
|
// Interrupt Clear
|
||
|
|
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
|
||
|
|
// Clear
|
||
|
|
#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt
|
||
|
|
// Clear
|
||
|
|
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
|
||
|
|
// Clear
|
||
|
|
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
|
||
|
|
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
|
||
|
|
// Interrupt Clear
|
||
|
|
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
|
||
|
|
// Interrupt Clear
|
||
|
|
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
|
||
|
|
// Interrupt
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAILR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
|
||
|
|
// Register
|
||
|
|
#define TIMER_TAILR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TBILR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
|
||
|
|
// Register
|
||
|
|
#define TIMER_TBILR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
|
||
|
|
#define TIMER_TAMATCHR_TAMR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
|
||
|
|
#define TIMER_TBMATCHR_TBMR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAPR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
|
||
|
|
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
|
||
|
|
#define TIMER_TAPR_TAPSRH_S 8
|
||
|
|
#define TIMER_TAPR_TAPSR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TBPR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
|
||
|
|
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
|
||
|
|
#define TIMER_TBPR_TBPSRH_S 8
|
||
|
|
#define TIMER_TBPR_TBPSR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
|
||
|
|
// Byte
|
||
|
|
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
|
||
|
|
#define TIMER_TAPMR_TAPSMRH_S 8
|
||
|
|
#define TIMER_TAPMR_TAPSMR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
|
||
|
|
// Byte
|
||
|
|
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
|
||
|
|
#define TIMER_TBPMR_TBPSMRH_S 8
|
||
|
|
#define TIMER_TBPMR_TBPSMR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
|
||
|
|
#define TIMER_TAR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TBR register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
|
||
|
|
#define TIMER_TBR_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAV register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
|
||
|
|
#define TIMER_TAV_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TBV register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
|
||
|
|
#define TIMER_TBV_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
|
||
|
|
#define TIMER_RTCPD_RTCPD_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_TAPS register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
|
||
|
|
#define TIMER_TAPS_PSS_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
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// The following are defines for the bit fields in the TIMER_O_TBPS register.
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//
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//*****************************************************************************
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#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
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#define TIMER_TBPS_PSS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_TAPV register.
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//
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//*****************************************************************************
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#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
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#define TIMER_TAPV_PSV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TIMER_O_TBPV register.
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//
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//*****************************************************************************
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#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
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#define TIMER_TBPV_PSV_S 0
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|
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||
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//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_DMAEV register.
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||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
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#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA
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||
|
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// Trigger Enable
|
||
|
|
#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger
|
||
|
|
// Enable
|
||
|
|
#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger
|
||
|
|
// Enable
|
||
|
|
#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA
|
||
|
|
// Trigger Enable
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_ADCEV register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger
|
||
|
|
// Enable
|
||
|
|
#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger
|
||
|
|
// Enable
|
||
|
|
#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger
|
||
|
|
// Enable
|
||
|
|
#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC
|
||
|
|
// Trigger Enable
|
||
|
|
#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC
|
||
|
|
// Trigger Enable
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_PP register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source
|
||
|
|
#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
|
||
|
|
#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
|
||
|
|
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
|
||
|
|
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
|
||
|
|
// 16 bits each with an 8-bit
|
||
|
|
// prescale counter
|
||
|
|
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
|
||
|
|
// 32 bits each with a 16-bit
|
||
|
|
// prescale counter
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the TIMER_O_CC register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source
|
||
|
|
|
||
|
|
#endif // __HW_TIMER_H__
|