419 lines
17 KiB
C
419 lines
17 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F7xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F7xx_MCUCONF
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#define STM32F746_MCUCONF
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#define STM32F756_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 432
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 9
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV4
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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#define STM32_RTCPRE_VALUE 25
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
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#define STM32_I2SSRC STM32_I2SSRC_OFF
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SDIVQ_VALUE 2
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIDIVQ_VALUE 2
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#define STM32_PLLSAIDIVR_VALUE 2
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF
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#define STM32_SAI2SEL STM32_SAI2SEL_OFF
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#define STM32_LCDTFT_REQUIRED FALSE
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#define STM32_USART1SEL STM32_USART1SEL_PCLK2
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#define STM32_USART2SEL STM32_USART2SEL_PCLK1
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#define STM32_USART3SEL STM32_USART3SEL_PCLK1
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#define STM32_UART4SEL STM32_UART4SEL_PCLK1
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#define STM32_UART5SEL STM32_UART5SEL_PCLK1
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#define STM32_USART6SEL STM32_USART6SEL_PCLK2
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#define STM32_UART7SEL STM32_UART7SEL_PCLK1
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#define STM32_UART8SEL STM32_UART8SEL_PCLK1
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
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#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_CECSEL STM32_CECSEL_LSE
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
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#define STM32_SRAM2_NOCACHE FALSE
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 15
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_PRIORITY 15
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#define STM32_IRQ_EXTI22_PRIORITY 15
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC2_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 FALSE
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#define STM32_CAN_USE_CAN2 FALSE
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#define STM32_CAN_USE_CAN3 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11
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#define STM32_CAN_CAN2_IRQ_PRIORITY 11
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#define STM32_CAN_CAN3_IRQ_PRIORITY 11
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/*
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* CRY driver system settings.
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*/
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#define STM32_CRY_USE_CRYP1 FALSE
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#define STM32_CRY_USE_HASH1 FALSE
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#define STM32_CRY_CRYP1_IRQ_PRIORITY 9
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#define STM32_CRY_HASH1_IRQ_PRIORITY 9
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#define STM32_CRY_HASH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_CRY_HASH1_DMA_PRIORITY 0
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#define STM32_CRY_HASH_SIZE_THRESHOLD 1024
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#define STM32_CRY_HASH_DMA_ERROR_HOOK(cryp) osalSysHalt("DMA failure")
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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#define STM32_GPT_USE_TIM12 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY 7
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#define STM32_GPT_TIM2_IRQ_PRIORITY 7
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#define STM32_GPT_TIM3_IRQ_PRIORITY 7
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#define STM32_GPT_TIM4_IRQ_PRIORITY 7
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#define STM32_GPT_TIM5_IRQ_PRIORITY 7
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#define STM32_GPT_TIM6_IRQ_PRIORITY 7
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#define STM32_GPT_TIM7_IRQ_PRIORITY 7
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#define STM32_GPT_TIM8_IRQ_PRIORITY 7
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#define STM32_GPT_TIM9_IRQ_PRIORITY 7
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#define STM32_GPT_TIM11_IRQ_PRIORITY 7
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#define STM32_GPT_TIM12_IRQ_PRIORITY 7
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#define STM32_GPT_TIM14_IRQ_PRIORITY 7
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_USE_I2C4 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C4_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_I2C4_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY 7
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#define STM32_ICU_TIM2_IRQ_PRIORITY 7
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#define STM32_ICU_TIM3_IRQ_PRIORITY 7
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#define STM32_ICU_TIM4_IRQ_PRIORITY 7
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#define STM32_ICU_TIM5_IRQ_PRIORITY 7
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#define STM32_ICU_TIM8_IRQ_PRIORITY 7
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#define STM32_ICU_TIM9_IRQ_PRIORITY 7
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/*
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* MAC driver system settings.
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*/
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#define STM32_MAC_TRANSMIT_BUFFERS 2
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#define STM32_MAC_RECEIVE_BUFFERS 4
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#define STM32_MAC_BUFFERS_SIZE 1522
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#define STM32_MAC_PHY_TIMEOUT 100
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#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
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#define STM32_MAC_ETH1_IRQ_PRIORITY 13
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#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM8 FALSE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY 7
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#define STM32_PWM_TIM2_IRQ_PRIORITY 7
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#define STM32_PWM_TIM3_IRQ_PRIORITY 7
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#define STM32_PWM_TIM4_IRQ_PRIORITY 7
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#define STM32_PWM_TIM5_IRQ_PRIORITY 7
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#define STM32_PWM_TIM8_IRQ_PRIORITY 7
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#define STM32_PWM_TIM9_IRQ_PRIORITY 7
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/*
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* RTC driver system settings.
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*/
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#define STM32_RTC_PRESA_VALUE 32
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#define STM32_RTC_PRESS_VALUE 1024
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#define STM32_RTC_CR_INIT 0
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#define STM32_RTC_TAMPCR_INIT 0
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/*
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* SDC driver system settings.
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*/
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#define STM32_SDC_USE_SDMMC1 FALSE
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#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
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#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
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#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
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#define STM32_SDC_SDMMC_CLOCK_DELAY 10
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#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
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#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_USART3 TRUE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 FALSE
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#define STM32_SERIAL_USE_USART6 FALSE
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#define STM32_SERIAL_USE_UART7 FALSE
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#define STM32_SERIAL_USE_UART8 FALSE
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#define STM32_SERIAL_USART1_PRIORITY 12
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#define STM32_SERIAL_USART2_PRIORITY 12
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#define STM32_SERIAL_USART3_PRIORITY 12
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#define STM32_SERIAL_UART4_PRIORITY 12
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#define STM32_SERIAL_UART5_PRIORITY 12
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#define STM32_SERIAL_USART6_PRIORITY 12
|
||
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|
#define STM32_SERIAL_UART7_PRIORITY 12
|
||
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|
#define STM32_SERIAL_UART8_PRIORITY 12
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SPI driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SPI_USE_SPI1 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI2 FALSE
|
||
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|
#define STM32_SPI_USE_SPI3 FALSE
|
||
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|
#define STM32_SPI_USE_SPI4 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI5 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI6 FALSE
|
||
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||
|
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||
|
|
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||
|
|
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||
|
|
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||
|
|
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
|
||
|
|
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||
|
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ST driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ST_IRQ_PRIORITY 8
|
||
|
|
#define STM32_ST_USE_TIMER 2
|
||
|
|
|
||
|
|
/*
|
||
|
|
* UART driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_UART_USE_USART1 FALSE
|
||
|
|
#define STM32_UART_USE_USART2 FALSE
|
||
|
|
#define STM32_UART_USE_USART3 FALSE
|
||
|
|
#define STM32_UART_USE_UART4 FALSE
|
||
|
|
#define STM32_UART_USE_UART5 FALSE
|
||
|
|
#define STM32_UART_USE_USART6 FALSE
|
||
|
|
#define STM32_UART_USE_UART7 FALSE
|
||
|
|
#define STM32_UART_USE_UART8 FALSE
|
||
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
|
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||
|
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||
|
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
|
|
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||
|
|
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||
|
|
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART7_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART8_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART7_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART8_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* USB driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_USB_USE_OTG1 FALSE
|
||
|
|
#define STM32_USB_USE_OTG2 FALSE
|
||
|
|
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||
|
|
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||
|
|
|
||
|
|
/*
|
||
|
|
* WDG driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_WDG_USE_IWDG FALSE
|
||
|
|
|
||
|
|
/*
|
||
|
|
* WSPI driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_WSPI_USE_QUADSPI1 FALSE
|
||
|
|
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
|
||
|
|
#endif /* MCUCONF_H */
|